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* gallium/swr: Fix depth values for blit scenarioJan Zielinski2019-10-311-0/+8
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* iris/gen11+: Move flush for render target changeJordan Justen2019-10-311-19/+20
| | | | | | | | | | | | | | When starting a BLORP operation, we do the BTI-change flush. However, when ending it and transitioning back to regular drawing, we change the render target again - without a set_framebuffer_state() call. We need to do the BTI flush there too. BLORP flags IRIS_DIRTY_RENDER_BUFFER now, which will cause the next draw to get the BTI flush again. (explanation of fix by Ken) Fixes: 2b956a093a1 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add IRIS_DIRTY_RENDER_BUFFER state flagJordan Justen2019-10-311-1/+3
| | | | | | Fixes: 2b956a093a1 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: declare NGG scratch for VS or TES and only on GFX10Samuel Pitoiset2019-10-311-5/+3
| | | | | | | | Do not need to declare it for other stages because this is for streamout. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* lima: add cubemap supportArno Messiaen2019-10-317-252/+45
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: introduce ppir_op_load_coords_reg to differentiate between loading ↵Arno Messiaen2019-10-316-5/+18
| | | | | | | | texture coordinates straight from a varying vs loading them from a register Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: add layer_stride field to lima_resource structArno Messiaen2019-10-313-15/+28
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: fix stride in texture descriptorArno Messiaen2019-10-312-3/+3
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* intel/compiler: Report the number of non-spill/fill SEND messages on vec4 tooIan Romanick2019-10-301-5/+35
| | | | | | | | | | | | | | | | | | This make shader-db's report.py work on Haswell and earlier platforms. The problem is that the script would detect the "sends" output for scalar shaders and expect in in vec4 shaders too. When it didn't find it, the script would fail with: Traceback (most recent call last): File "./report.py", line 351, in <module> main() File "./report.py", line 182, in main before_count = before[p][m] KeyError: 'sends' Fixes: f192741ddd8 ("intel/compiler: Report the number of non-spill/fill SEND messages") Reviewed-by: Kenneth Graunke <[email protected]>
* nir: fix couple of compile warningsTapani Pälli2019-10-311-2/+2
| | | | | | | Fixes "warning: braces around scalar initializer" warnings. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: Fix timeout handling in syncobj wait.Bas Nieuwenhuizen2019-10-311-1/+1
| | | | | | | libdrm returns -errno instead of directly the ioctl ret of -1. Fixes: 1c3cda7d277 "radv: Add syncobj signal/reset/wait to winsys." Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: mark STORE destination inputs as usedIlia Mirkin2019-10-301-0/+6
| | | | | | | | | | Observed an issue when looking at the code generatedy by the image-vertex-attrib-input-output piglit test. Even though the test itself worked fine (due to TIC 0 being used for the image), this needs to be fixed. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gm107/ir: fix loading z offset for layered 3d image bindingsIlia Mirkin2019-10-304-54/+202
| | | | | | | | | | | | | | | | | | | | | | | | Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate code. As a result all plain 2d loads are converted into a pair of 2d/3d loads, with appropriate predicates to ensure only one of those actually executes, and the values are all merged in. This goes somewhat against the current flow, so for GM107 we do the OOB handling directly in the surface processing logic. Perhaps the other gens should do something similar, but that is left to another change. This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS tests like shader_image_load_store.non-layered_binding without breaking anything else. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "20.0" <[email protected]>
* intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin2019-10-301-1/+2
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake") Acked-by: Jason Ekstrand <[email protected]>
* docs/new_features: Empty the feature list for the 20.0 cycleDylan Baker2019-10-301-18/+0
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* Bump VERSION to 20.0.0-develDylan Baker2019-10-301-1/+1
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* docs/relnotes/new_features.txt: Add note about gen12 support19.3-branchpointJordan Justen2019-10-301-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* intel/eu/validate/gen12: Add TGL to eu_validate tests.Jordan Justen2019-10-301-0/+9
| | | | | | | | | | | | These reworks were combined into this patch: * Matt Turner: i965: Disable NoDDChk/NoDDClr test on Gen12+ * Francisco Jerez: intel/eu/validate/gen12: Disable qword_low_power_no_depctrl eu_validate test. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dev: Add preliminary device info for TigerlakeJordan Justen2019-10-302-0/+56
| | | | | | | | | | | Reworks: * adjust 64-bit support, hiz (Jason Ekstrand) * sim-id (Lionel Landwerlin) * adjust threads, urb size (Rafael Antognolli) * adjust urb size (Kenneth Graunke) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dump_gpu: handle context create extended ioctlLionel Landwerlin2019-10-301-0/+15
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radv: Allocate space for temp. semaphore parts.Bas Nieuwenhuizen2019-10-301-0/+1
| | | | | | | | Calculated the number for allocation and did not reserve space .... Fixes: 2117c53b723 "radv: Add temporary datastructure for submissions." Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-303-1/+45
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* blorp: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-301-0/+3
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* iris: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-302-0/+21
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* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* aco: implement VGPR spillingDaniel Schürmann2019-10-301-7/+162
| | | | | | VGPR spilling is implemented via MUBUF instructions and scratch memory. Reviewed-by: Rhys Perry <[email protected]>
* aco: always set scratch_offset in startpgmDaniel Schürmann2019-10-303-23/+22
| | | | | | | This patch also moves private_segment_buffer and scratch_offset to Program to easily access it. Reviewed-by: Rhys Perry <[email protected]>
* aco: omit linear VGPRs as spill variablesDaniel Schürmann2019-10-301-4/+8
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: ensure that spilled VGPR reloads are done after p_logical_startDaniel Schürmann2019-10-301-34/+43
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: simplify calculation of target register pressure when spillingDaniel Schürmann2019-10-301-39/+12
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: fix new_demand calculation for first instructionsRhys Perry2019-10-301-4/+7
| | | | Reviewed-by: Daniel Schürmann <[email protected]>
* aco: don't add interferences between spilled phi operandsDaniel Schürmann2019-10-301-8/+8
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: consider loop_exit blocks like merge blocks, even if they have only one ↵Daniel Schürmann2019-10-301-2/+2
| | | | | | predecessor Reviewed-by: Rhys Perry <[email protected]>
* aco: don't insert the exec mask into set of live-out variables when spillingDaniel Schürmann2019-10-301-14/+6
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: fix transitive affinities of spilled variablesDaniel Schürmann2019-10-301-25/+79
| | | | | | | Variables spilled on both branch legs need to be assigned to the same spilling slot. These affinities can be transitive through multiple merge blocks. Reviewed-by: Rhys Perry <[email protected]>
* aco: fix live-range splits of phisDaniel Schürmann2019-10-301-14/+23
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: remove potential critical edge on loops.Daniel Schürmann2019-10-302-18/+23
| | | | Reviewed-by: Rhys Perry <[email protected]>
* aco: improve live variable analysisDaniel Schürmann2019-10-301-25/+64
| | | | | | | This patch makes the live variable analysis more precise w.r.t. killed phi operands and the block's register pressure. Reviewed-by: Rhys Perry <[email protected]>
* aco: Lower to CSSADaniel Schürmann2019-10-304-41/+268
| | | | | | | | | | Converting to 'Conventional SSA Form' ensures correctness w.r.t. spilling of phi nodes. Previously, it was possible that phi operands have intersecting live-ranges, and thus, couldn't get spilled to the same spilling slot. For this reason, ACO tried to avoid to spill phis, even if it was beneficial. This patch implements a conversion pass which is currently only called if spilling is necessary. Reviewed-by: Rhys Perry <[email protected]>
* etnaviv: fix non-pointsprite points on GC7000LJonathan Marek2019-10-301-0/+4
| | | | | | | | | | | | | Fixes these deqp tests (and more): dEQP-GLES2.functional.draw.draw_arrays.points.single_attribute dEQP-GLES2.functional.draw.draw_arrays.points.multiple_attributes dEQP-GLES2.functional.draw.draw_arrays.points.default_attribute dEQP-GLES2.functional.draw.draw_elements.points.single_attribute dEQP-GLES2.functional.draw.draw_elements.points.multiple_attributes dEQP-GLES2.functional.draw.draw_elements.points.default_attribute Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: stencil fixJonathan Marek2019-10-301-13/+15
| | | | | | | | | | | | | | | The final version of previous stencil fix patch ended up breaking one-sided stencil. Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L): dEQP-GLES2.functional.fragment_ops.depth_stencil.* Note: deqp tests require --deqp-gl-config-name=rgba8888d24s8ms0 Fixes: 05da025f ("etnaviv: fix two-sided stencil") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix depth biasJonathan Marek2019-10-302-1/+2
| | | | | | | | | | Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L): dEQP-GLES2.functional.polygon_offset.* Fixes: 6c3c05dc ("etnaviv: fix polygon offset") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* iris: Set MOCS for external surfaces to uncachedJordan Justen2019-10-301-4/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* iris: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+5
| | | | | | | | | | | | | | | On gen11 and older, compressed images are tiled and aligned to 4K. On gen12 this 4K alignment restriction was removed. However, only aligning the fast clear color buffer to 64B (a cacheline, as it's on the documentation) is causing some bugs where the fast clear color is not converted during the fast clear operation. Aligning things to 4K seems to fix it. v2: Fix typo case in the comment (Nanley) v3: Rebase and fix conflicts. v4: Fix rebase mistake (Nanley). Reviewed-by: Nanley Chery <[email protected]>
* anv: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+9
| | | | | | | | | | | | | On gen11 and older, compressed images are tiled and aligned to 4K. On gen12 this 4K alignment restriction was removed. However, only aligning the fast clear color buffer to 64B (a cacheline, as it's on the documentation) is causing some bugs where the fast clear color is not converted during the fast clear operation. Aligning things to 4K seems to fix it. v2: Assert that image->planes[plane].offset is 4K aligned (Nanley) Reviewed-by: Nanley Chery <[email protected]>
* zink: only enable KHR_external_memory_fd if supportedErik Faye-Lund2019-10-303-7/+28
| | | | | | | | While we're at it, make sure we error out if it's not supported when required. This brings us a bit closer to being able to test on SwiftShader, which doesn't currently support KHR_external_memory_fd.
* radv: Start signalling semaphores in WSI acquire.Bas Nieuwenhuizen2019-10-301-7/+27
| | | | | | | | | | Winsys semaphores without signal operation get silently ignored. Not so for syncobjs, so actually signal them. Fixes: 84d9551b232 "radv: Always enable syncobj when supported for all fences/semaphores." Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2030 Reviewed-by: Samuel Pitoiset <[email protected]>
* aco: rename README to README.mdRhys Perry2019-10-301-0/+0
| | | | | Closes: #1974 Signed-off-by: Rhys Perry <[email protected]>
* aco: a couple loop handling fixes for GFX10 hazard passRhys Perry2019-10-301-3/+3
| | | | | | | It was joining from the wrong blocks and block.kind is a bitmask instead of an enum. Reviewed-By: Timur Kristóf <[email protected]>
* intel/compiler: Add instruction compaction support on Gen12Matt Turner2019-10-302-184/+868
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
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