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* intel: Fix the description of Coffeelake pci-id 0x3E98Jian-Hong Pan2019-04-101-1/+1
| | | | | | | | | | | | | | | | | According to Intel website [1], the description of chipset 8086:3E98 is Intel(R) UHD Graphics 630. Besides, xserver also mentions it as "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)" in commit d3a26bbf (DRI2: Add another Coffeelake PCI ID) [2]. This patch modifies the description to sync with xserver. [1]: https://ark.intel.com/content/www/us/en/ark/products/134896/intel-core-i5-9600k-processor-9m-cache-up-to-4-60-ghz.html [2]: https://gitlab.freedesktop.org/xorg/xserver/commit/d3a26bbf618507e1ca05b2bc99a880075b77db77 Fixes: commit 44f1dcf9b3fd "i965: Add a new CFL PCI ID." Signed-off-by: Jian-Hong Pan <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Anuj Phogat [email protected]
* Partially revert "gallium: fix autotools build of pipe_msm.la"Jan Vesely2019-04-101-1/+2
| | | | | | | | | | | | This partially reverts commit 356ec7a21960d77db282f67af577dcdb46966b5a. There are symbols needed by libglsl missing, so we might as well skip the entire library. Fixes: 356ec7a21960d77db282f67af577dcdb46966b5a Signed-off-by: Jan Vesely <[email protected]> Acked-by: Dieter Nützel <[email protected]> Tested-by: Dieter Nützel <[email protected]> Tested-by: Vinson Lee <[email protected]>
* vc4: Upload CS/VS UBO uniforms together.Eric Anholt2019-04-105-181/+22
| | | | | | | | | | | | | | | | | Same as I did for V3D, drop all this code trying to GC the non-indirectly-loaded uniforms from the UBO that's used for indirect access of gallium cb[0]. While it does successfully drop some of those, it came at the cost of uploading the VS's indirect unifroms twice, for the bin and render versions of the shader. With the UBO loads simplified, I was also able to easily backport V3D's change to pack a UBO offset into the uniform_data[] field so that we don't need to do the add of the uniform base in the shader. As a bonus, now vc4 doesn't depend on mesa/st type_size functions. total uniforms in shared programs: 25514 -> 25490 (-0.09%) total instructions in shared programs: 77019 -> 76836 (-0.24%)
* vc4: Split UBO0 and UBO1 address uniform handling.Eric Anholt2019-04-103-19/+20
| | | | I'm going to extend how UBO0 works in a moment.
* vc4: Don't forget to set the range when scalarizing our uniforms.Eric Anholt2019-04-101-0/+2
| | | | | | In the next commit, we'll want this for handling UBO access clamping. Reviewed-by: Kenneth Graunke <[email protected]>
* st: Lower uniforms in st in the !PIPE_CAP_PACKED_UNIFORMS case as well.Eric Anholt2019-04-107-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | PIPE_CAP_PACKED_UNIFORMS conflates several things: Lowering uniforms i/o at the st level instead of the backend, packing uniforms with no padding at all, and lowering to UBOs. Requiring backends to lower uniforms i/o for !PIPE_CAP_PACKED_UNIFORMS leads to the driver needing to either link against the type size function in mesa/st, or duplicating it in the backend. Given that all backends want this lower-io as far as I can tell, just move it to mesa/st to resolve the link issue and avoid the driver author needing to understand st's uniforms layout. Incidentally, fixes uniform layout failures in nouveau in: dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_fragment dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_vertex and I think in Lima as well. v2: fix indents Reviewed-by: Kenneth Graunke <[email protected]>
* anv: don't use default pipeline cache for hits for ↵Lionel Landwerlin2019-04-101-1/+1
| | | | | | | | | | | | | VK_EXT_pipeline_creation_feedback If the user didn't provide a pipeline cache and we're using the default internal pipeline cache, then we shouldn't consider a cache hit for VK_EXT_pipeline_creation_feedback as the application did not provide a cache. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 6601e5d6fc68cd ("anv: implement VK_EXT_pipeline_creation_feedback") Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "glsl: fix shader_storage_blocks_write_access for SSBO block arrays"Marek Olšák2019-04-101-6/+2
| | | | | | This reverts commit b7ca074cc0df6101c428b2dfa53a59a0c6620af2. It broke a lot of tests.
* glsl/standalone: add GLES3.1 and GLES3.2 compatibilityKarol Herbst2019-04-101-0/+5
| | | | | | | | | | also set some constants for SSBOs. With that it can compile the shader from: dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.18 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* virgl: use debug_printf instead of fprintfErik Faye-Lund2019-04-101-1/+1
| | | | | | | | | While we're at it, prefix the string with "VIRGL: ", to match similar code elsewhere in virgl. Fixes: d7b31969767 ("virgl: Return an error if we use fp64 on top of GLES") Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Elie Tournier <[email protected]>
* virgl: Enable passing arrays as input to fragment shadersGert Wollny2019-04-103-7/+64
| | | | | | | | | | | | | | | | | | | This is needed to properly handle interpolateAt* when the input to be interpolated is passed as array in the original GLSL. Currently, the the GLSL compiler would lower selecting the correct input so that the interpolant parameter to interpolateAt* is a temporary, and this can not be used to create a valid shader on the host side, because here the parameter must a shader input. By allowing the passing the created TGSI allows to create proper GLSL. This is related to the virglrenderer bug https://gitlab.freedesktop.org/virgl/virglrenderer/issues/74 v2: Squash the two patches handling these flags into another Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* Gallium: Add new CAP that indicated whether IO array definitions can be shrikedGert Wollny2019-04-103-0/+6
| | | | | | | | | PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS is added to indicate whether the TGSI pass to shrink IO arrays should be skipped to enforce the originally declared array sizes and locations instead. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* wsi: allow to override the present mode with MESA_VK_WSI_PRESENT_MODESamuel Pitoiset2019-04-106-3/+78
| | | | | | | This is common to all Vulkan drivers and all WSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: enable VK_AMD_gpu_shader_half_floatSamuel Pitoiset2019-04-101-0/+1
| | | | | | | | Should be safe to enable as all instructions seem to support 16-bit. Unfortunately, there is no CTS test. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 16-bit support to ac_build_ddxy()Rhys Perry2019-04-101-5/+17
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: fix nir_op_b2f16Samuel Pitoiset2019-04-101-3/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: Set bind when creating temp resource.Lepton Wu2019-04-091-0/+10
| | | | | | | | | virgl render complains about "Illegal resource" when running dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_window, the reason is that a zero bind value was given for temp resource. Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* radv: Add non-uniform indexing lowering.Bas Nieuwenhuizen2019-04-102-7/+12
| | | | | | | | | This patch does it as late as possible so the potential extra basic blocks don't inhibit other optimizations. Big thanks to Jason for writing the lowering pass. Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: Add access qualifiers on load_ubo intrinsic.Bas Nieuwenhuizen2019-04-102-2/+3
| | | | | | | | | Otherwise nir_lower_non_uniform_access crashes when it tries to get the access of a load_ubo. Fixes: 8ed583fe523 "spirv: Handle the NonUniformEXT decoration" Fixes: e50ab2c0f23 "nir: Add access flags to deref and SSBO atomics" Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: fix shader_storage_blocks_write_access for SSBO block arraysMarek Olšák2019-04-091-2/+6
| | | | | | | | CTS: GL45-CTS.compute_shader.resources-max Fixes: 4e1e8f684bf "glsl: remember which SSBOs are not read-only and pass it to gallium" Reviewed-by: Timothy Arceri <[email protected]>
* freedreno: PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT unreachable statementKhaled Emara2019-04-091-1/+0
| | | | | | | There seems to be a duplicate return statement, as A2XX doesn't support shader buffers. Reviewed-by: Rob Clark <[email protected]>
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-0910-21155/+21105
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* genxml: add a sorting scriptLionel Landwerlin2019-04-093-0/+203
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* bin: drop unused import from install_megadrivers.pyEric Engestrom2019-04-091-1/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* anv: advertise 8 subtexel/mipmap precision bitsJuan A. Suarez Romero2019-04-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far ANV was advertising 4 bits for both subTexelPrecisionBits and mipmapPrecisionBits. But these values were not actually verified. But it seems the right value is actually 8 bits for both cases. Unfortunately Intel PRM does not clarify how many bits the hardware use. For the mipmap case, there is the following reference in PRM Volume 6 (3D Media GPGPU), specifically in LOD Computation Pseudocode: ``` Bias: S4.8 MinLod: U4.8 MaxLod: U4.8 Base: U4.1 MIPCnt: U4 SurfMinLod: U4.8 ResMinLod: U4.8 `` We have other clues, though: - On one side, dEQP-VK.texture.explicit_lod.* tests fail when using 4 bits, but work when using 8 bits. These tests try to mimic the expected behaviour as much real as possible, and they use the reported subTexelPrecisionBits and mipmapPrecisionBits reported to get this. - On the other side, the equivalent driver for Windows is reporting 8 bits for both elements. Not sure if they got to verify it from the PRM or from a diffent source. CC: Jason Ekstrand <[email protected]> CC: Lionel Landwerlin <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* st/va: reverse qt matrix back to its original orderBoyuan Zhang2019-04-091-6/+32
| | | | | | | | | | | | The quantiser matrix that VAAPI provides has been applied with inverse z-scan. However, what we expect in MPEG2 picture description is the original order. Therefore, we need to reverse it back to its original order. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110257 Cc: [email protected] Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]>
* glsl/linker: location aliasing requires types to have the same widthAndres Gomez2019-04-091-39/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the OpenGL 4.60.5 spec, section 4.4.1 Input Layout Qualifiers, Page 67, (Location aliasing): " Further, when location aliasing, the aliases sharing the location must have the same underlying numerical type and bit width (floating-point or integer, 32-bit versus 64-bit, etc.) and the same auxiliary storage and interpolation qualification." Additionally, we have improved the linker error descriptions. Specifically, when taking structs into account we were producing a linker error because we assumed that all components in each location were used and that would cause component aliasing. This is not accurate of the actual problem. Now, the failure specifies that the underlying numerical type incompatibility is the cause for the failure. Fixes the following piglit test: tests/spec/arb_enhanced_layouts/linker/component-layout/vs-to-fs-width-mismatch-double-float.shader_test v2: - Do not assert if we see invalid numerical types. These come straight from shader code, so we should produce linker errors if shaders attempt to do location aliasing on variables that are not numerical such as records. - While we are at it, improve error reporting for the case of numerical type mismatch to include the shader stage. v3: - Allow location aliasing of images and samplers. If we get these it means bindless support is active and they should be handled as 64-bit integers (Ilia) - Make sure we produce link errors for any non-numerical type for which we attempt location aliasing, not just structs. v4: - Rebased with minor fixes (Andres). - Added fixing tag to the commit log (Andres). v5: - Remove the helper function and check individually for the underlying numerical type and bit width (Timothy). - Implicitly, assume that any non-treated type which is checked for its underlying numerical type is either integer or float and has a defined bit width (Timothy). - Implicitly, assume that structs are the only non-treated non-numerical type (Timothy). - Improve the linker error descriptions and commit log (Andres). Fixes: 13652e7516a ("glsl/linker: Fix type checks for location aliasing") Cc: Ilia Mirkin <[email protected]> Cc: Timothy Arceri <[email protected]> Cc: Iago Toral Quiroga <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* softpipe: Enable PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENTGert Wollny2019-04-092-2/+2
| | | | | | | | | | | | | The offset alignment must be set to s16 because the tile cache is implemented to require this. This enables ARB_buffer_texture_range and OES_texture_buffer for softpipe. The according deqp-gles31 tests pass. Also update the feature table. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* softpipe: Add an extra code path for the buffer texel lookupGert Wollny2019-04-091-1/+16
| | | | | | | | | | With buffers the addressing is done on a per-byte bases so the code path for normal textures doesn't work properly. Also add an assert to make sure that the bit cound for storing the X coordinate is large enough. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* softpipe: raise number of bits used for X coordinate texture lookupGert Wollny2019-04-092-7/+6
| | | | | | | | | With buffers the addressing is done on a per byte basis and we with a maximal block size of 16 byte we have to take into acount four more bits. For simplicity just remove the TEX_TILE_SIZE_LOG2, which is 5 bit. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* softpipe: Don't use mag filter for gather opGert Wollny2019-04-091-3/+3
| | | | | | | | | | | For the gather op no magnifictaion filter is provided, so always use the filter given for minification (which is the linear filter) Fixes: 0dff1533f25951adda3c36be6d9efa944741befb softpipe: Use mag texture filter also for clamped lod == 0 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nir: Get rid of global registersJason Ekstrand2019-04-0918-209/+10
| | | | | | | | | We have a pass to lower global registers to locals and many drivers dutifully call it. However, no one ever creates a global register ever so it's all dead code. It's time we bury it. Acked-by: Karol Herbst <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Get rid of nir_register::is_packedJason Ekstrand2019-04-097-34/+11
| | | | | | | | All we ever do is initialize it to zero, clone it, print it, and validate it. No one ever sets or uses it. Acked-by: Karol Herbst <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* virgl: add support for ARB_indirect_parametersDave Airlie2019-04-093-2/+4
| | | | | | The protocol changes are already in place for it. Reviewed-By: Gert Wollny <[email protected]>
* virgl: add support for ARB_multi_draw_indirectDave Airlie2019-04-093-5/+10
| | | | | | | This will pass the multi draw through to the host if it has support for it instead of using the st to emulate it Reviewed-By: Gert Wollny <[email protected]>
* virgl: add support for missing command buffer binding.Dave Airlie2019-04-093-3/+9
| | | | | | | When I added indirect support I forgot this, however to use it now we need to check for a new enough capability on the host side. Reviewed-By: Gert Wollny <[email protected]>
* docs: Add NV_compute_shader_derivatives to 19.1.0 relnotesCaio Marcelo de Oliveira Filho2019-04-081-0/+2
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* anv: Implement VK_NV_compute_shader_derivativesCaio Marcelo de Oliveira Filho2019-04-083-0/+10
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add support for DerivativeGroup capabilitiesCaio Marcelo de Oliveira Filho2019-04-082-0/+16
| | | | | | | | | | | | As defined in SPV_NV_compute_shader_derivatives. These control how the invocations are arranged in a CS when doing derivative and related operations (which are also enabled by the extension). Since we expect valid SPIR-V, we don't need to do more work at SPIR-V level to enable the derivative and related operations to be called. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Enable NV_compute_shader_derivativesCaio Marcelo de Oliveira Filho2019-04-081-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* gallium: Add PIPE_CAP_COMPUTE_SHADER_DERIVATIVESCaio Marcelo de Oliveira Filho2019-04-084-0/+6
| | | | | | | | To enable NV_compute_shader_derivatives, which allows derivatives (and texture lookups with implicit derivatives) in compute shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Advertise NV_compute_shader_derivativesCaio Marcelo de Oliveira Filho2019-04-081-0/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* intel/fs: Use NIR_PASS_V when lowering CS intrinsicsCaio Marcelo de Oliveira Filho2019-04-081-3/+4
| | | | | | | | | This will make that step visible in NIR_PRINT=1. v2: Also use the macro for the cleanup passes. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Don't loop when lowering CS intrinsicsCaio Marcelo de Oliveira Filho2019-04-081-15/+10
| | | | | | | | | This was needed when certain intrinsics were lowered to other ones that were defined by the same pass. After 060817b2 "intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_values" we don't need the loop anymore. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Add support for CS to group invocations in quadsCaio Marcelo de Oliveira Filho2019-04-083-16/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using quads, instead of mapping the elements to the next 4 local invocation indices, we map the two next in the "current" row and two next in the "next row". A side effect is that a thread will execute the indices in a different order. We now perform the lowering of both local invocation ID and index together -- and don't rely anymore on lowering done by nir_lower_system_values. That is convenient when doing the math for quads, because we need X and Y to get the right invocation index. When the pass progresses, fold the constants and clean up to reduce the noise from the indexing math. This implements the derivative_group_quadsNV semantics from NV_compute_shader_derivatives. v2: Take subgroup_id into account, otherwise only values in the first subgroup would be used. (Jason) v3: Calculate invocation index and ID together, to avoid duplicating some math in the quads case when both index and ID are used. (Jason) v4: Don't call cleanup passes as part of the lowering, let that to the call site. (Jason) Change calculation to use less instructions. (Jason) Reviewed-by: Ian Romanick <[email protected]> (v3) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Use TEX_LOGICAL whenever implicit lod is supportedCaio Marcelo de Oliveira Filho2019-04-081-2/+6
| | | | | | | Make sure we include compute shaders that have a derivative group defined. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Don't set LOD=0 for compute shader that has derivative groupCaio Marcelo de Oliveira Filho2019-04-081-2/+6
| | | | | | | | | | | When using NV_compute_shader_derivatives to set a derivative group, a compute shader supports texture with implicit LOD calculation, so don't set an explicit LOD. Note if the extension is used but the derivative group is not specified, it will default to LOD=0 as before. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/algebraic: Lower CS derivatives to zero when no group definedCaio Marcelo de Oliveira Filho2019-04-082-0/+14
| | | | | | | | | | | In compute shaders if no derivative group is defined, the derivatives will always be zero. Specified in NV_compute_shader_derivatives. To make the check more convenient, add a "info" local variable to the generated code so we can refer to it in the Python rules. (Jason) Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Parse and propagate derivative_group to shader_infoCaio Marcelo de Oliveira Filho2019-04-089-4/+193
| | | | | | | | | | | | NV_compute_shader_derivatives allow selecting between two possible arrangements (quads and linear) when calculating derivatives and certain subgroup operations in case of Vulkan. So parse and propagate those up to shader_info.h. v2: Do not fail when ARB_compute_variable_group_size is being used, since we are still clarifying what is the right thing to do here. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Enable texture builtins for NV_compute_shader_derivativesCaio Marcelo de Oliveira Filho2019-04-081-140/+153
| | | | | | | Renamed a few predicates from "fs_only" to be "derivative_only" (or similar pairs). Reviewed-by: Ian Romanick <[email protected]>
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