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* vulkan: Drop vk_android_native_buffer.xmlJason Ekstrand2018-04-1012-109/+26
| | | | | | | | All the information in vk_android_native_buffer.xml is now in vk.xml. The only exception is the extension type attribute which we can work around in the generators while we wait for the XML to be fixed. Reviewed-by: Dylan Baker <[email protected]>
* nir/lower_atomics: Rework the main walker loop a bitJason Ekstrand2018-04-101-8/+16
| | | | | | | | This replaces some "if (...} { }" with "if (...) continue;" to reduce nesting depth and makes nir_metadata_preserve conditional on progress for the given impl. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* radv: Enable RB+ where possible.Bas Nieuwenhuizen2018-04-113-6/+151
| | | | | | | | | | | | | | | According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent on the format which mean we would have to have more pipelines for the meta shaders. v2: Don't clear RB+ regs if not enabled as the CLEAR_STATE packet does already. Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: Check if u_vector_init() succeedsTopi Pohjolainen2018-04-111-2/+9
| | | | | | | | | | | However, it only fails when running out of memory. Now, if we are about to check that, we should be consistent and check the allocation of the worklist as well. CID: 1433512 Fixes: edb18564c7 nir: Initial implementation of a nir_instr_worklist Reviewed-by: Thomas Helland <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* mesa: Assert base format before truncating to unsigned shortTopi Pohjolainen2018-04-111-2/+3
| | | | | | | | | CID: 1433709 Fixes: ca721b3d8: mesa: use GLenum16 in a few more places Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/dev: Assert the number of slices is not zeroTopi Pohjolainen2018-04-111-1/+1
| | | | | | | Fixes: c1900f5b intel: devinfo: add helper functions to fill... CID: 1433511 Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.Kenneth Graunke2018-04-101-10/+4
| | | | | | I'd like to drop this pre-isl function. This drops one of the two uses. Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: fix glsl version mismatch in compat profileTimothy Arceri2018-04-111-2/+6
| | | | | | | | | | Drivers that only support compat 3.0 were reporting GLSL 1.40 support. This fixes issues with the menu of Dawn of War II. Fixes: a0c8b49284ef "mesa: enable OpenGL 3.1 with ARB_compatibility" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105807
* radv: fix picking the method for resolve subpassSamuel Pitoiset2018-04-101-1/+1
| | | | | | | | | | | The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add shader BOs to the list at pipeline bind timeSamuel Pitoiset2018-04-101-3/+15
| | | | | | | | | | | | Otherwise, the shader BOs are not added to the list on SI because prefetching isn't supported. Calling radv_cs_add_buffer() in the prefetch codepath was a bad idea. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105952 Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2") Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Turo Lamminen <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: don't set the display flag for obviously unsupported cases (v2)Marek Olšák2018-04-104-4/+33
| | | | | | | This enables the tile swizzle for some cases of the displayable micro mode, and it also fixes an addrlib assertion failure on Vega. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add shader binary padding for UMRMarek Olšák2018-04-101-3/+15
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* ac/surface/gfx9: request desired micro tile mode explicitlyMarek Olšák2018-04-101-4/+16
| | | | Tested-by: Dieter Nützel <[email protected]>
* docs/release-calendar: update to include 18.1 and 18.2Emil Velikov2018-04-101-4/+84
| | | | | | | | | | | | | | Dylan has kindly stepped up to help with 18.1.0, while I've taken the liberty to nominate Andres for 18.2.0 ;-) As always, people are welcome to swap/adjust where needed. v2: Add Juan for 18.0.x (Juan) Cc: Andres Gomez <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]> Acked-by: Dylan Baker <[email protected]> (v1) Signed-off-by: Emil Velikov <[email protected]>
* glsl: remove unreachable assert()Emil Velikov2018-04-101-2/+0
| | | | | | | | | | Earlier commit enforced that we'll bail out if the number of terminators is different than 2. With that in mind, the assert() will never trigger. Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop unrolling pass") Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* spirv: autotools: add vtn_gather_types_c.py in distribution tarballJuan A. Suarez Romero2018-04-101-1/+2
| | | | | | | Fixes: 042ee4bea26 "(spirv: Move SPIR-V building to Makefile.spirv.am and spirv/meson.build") Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: autotools: add si_build_pm4.h in dist tarballJuan A. Suarez Romero2018-04-101-0/+1
| | | | | | | | Fixes: 5777488406c ("radeonsi: move r600_cs.h contents into si_pipe.h, si_build_pm4.h") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* ac/nir: Use an array instead of hashtable for SSA defs.Bas Nieuwenhuizen2018-04-101-9/+13
| | | | | | | | | Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: finalise tcs/tes/geom NIR before storing it to the cacheTimothy Arceri2018-04-101-2/+9
| | | | | | | We don't create variants of the NIR so here we finalise it before caching to avoid unnecessary processing when restoring it. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: exit st_translate_fragment_program() earlier for NIR pathTimothy Arceri2018-04-101-6/+6
| | | | | | This avoids a bunch of scanning that is only used by the TGSI path. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: tidy up si_nir_load_sampler_desc()Timothy Arceri2018-04-101-5/+3
| | | | | | | | This makes it easier to follow the code, and also initialises dynamic_index which will be useful for adding bindless textures support. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set uses_bindless_images for imagesTimothy Arceri2018-04-101-1/+16
| | | | | | V2: add missing intrinsics (Spotted-by: Samuel Pitoiset) Reviewed-by: Marek Olšák <[email protected]>
* nir: dont lower bindless samplersTimothy Arceri2018-04-101-1/+7
| | | | | | | We neeed to skip the var if its not a uniform here as well as checking the bindless flag since UBOs can contain bindless samplers. Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: set paramater value offset as driver location for packed ↵Timothy Arceri2018-04-103-11/+11
| | | | | | | | | uniforms This allows us to simplify the code and will also be useful for supporting bindless textures. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: don't add bindless samplers/images to declared bitmasksTimothy Arceri2018-04-101-6/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: stop calling _mesa_init_shader_object_functions()Timothy Arceri2018-04-101-1/+0
| | | | | | | This sets the LinkShader function for the driver, but for the st we set it properly with the following call to st_init_program_functions(). Reviewed-by: Marek Olšák <[email protected]>
* anv/pipeline: Lower more constant initializers earlierJason Ekstrand2018-04-091-7/+5
| | | | | | | | Once we've gotten rid of everything but the main entrypoint, there's no reason why we should go ahead and lower them all. This is what radv does and it will make future work easier. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Use the LOCAL_GROUP_SIZE system valueJason Ekstrand2018-04-091-15/+2
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir/lower_system_values: Support SYSTEM_VALUE_LOCAL_GROUP_SIZEJason Ekstrand2018-04-091-0/+10
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel: aubinator: print out addresses of invalid instructionsLionel Landwerlin2018-04-101-9/+14
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* radv: Always reset draw user SGPRs after secondary command buffer.Bas Nieuwenhuizen2018-04-091-14/+3
| | | | | | | | As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't set instance count using predication.Bas Nieuwenhuizen2018-04-091-1/+1
| | | | | | | | | | The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa/st/nir: fix instruction removalRob Clark2018-04-091-1/+1
| | | | | | | | | At one point this kinda worked (or at least didn't cause problems). But with deref-instructions it results in dangling deref instructions not being properly removed. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/st/nir: fix naked lowering pass callRob Clark2018-04-091-1/+1
| | | | | | | | Not using the macro means no nir_validate in debug builds, resulting in problems showing up only after later passes. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: add comment about nir_src_copy()Rob Clark2018-04-091-0/+3
| | | | | | | So it is more clear about when to use nir_instr_rewrite_src() Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make the miptree clear color setter take a gl_color_unionNanley Chery2018-04-093-6/+7
| | | | | | | | We want to hide the internal details of how the miptree's clear color is calculated. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Move the clear color and value setter implementationsNanley Chery2018-04-092-21/+30
| | | | | | | These will get more complex in later commits. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use the brw_context for the clear color and value settersNanley Chery2018-04-093-6/+6
| | | | | | | Do what all the other functions in the miptree API do. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: convert dispatch packet to little endianBas Vermeulen2018-04-091-12/+12
| | | | | | | | | | | | | | | The parameters for the compute engine are wrong when using an E8860 on a big endian machine. To fix this, convert the contents of struct dispatch_packet to little endian. This ensures that get_global_id(0) and similar functions in the OpenCL code get the correct endian values, and makes my simple OpenCL program work correctly. Signed-off-by: Bas Vermeulen <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: correct si_vgt_param_key on big endian machinesBas Vermeulen2018-04-091-0/+13
| | | | | | | | | | | | Using mesa OpenCL failed on a big endian PowerPC machine because si_vgt_param_key is using bitfields and a 32 bit int for an index into an array. Fix si_vgt_param_key to work correctly on both little endian and big endian machines. Signed-off-by: Bas Vermeulen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: don't set RB+ registers on GFX9 chips without RB+Marek Olšák2018-04-091-6/+1
| | | | | | CLEAR_STATE initializes them properly. Reviewed-by: Samuel Pitoiset <[email protected]>
* etnaviv: meson: add etnaviv_query_pm.[ch] to the sourcesEmil Velikov2018-04-091-0/+2
| | | | | | | | | | | Otherwise building the driver will fail with unresolved symbols. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105960 Fixes: 72d2043be06 ("etnaviv: add perfmon query implementation") Cc: Christian Gmeiner <[email protected]> Cc: Clayton Craft <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* i965: return the fourcc saved in __DRIimage when possibleXiong, James2018-04-091-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a image from a texture, the image's dri_format is set to the first plane's format, and used to look up for the fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function intel_lookup_fourcc(): { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, instead of the correct one: { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned. To fix this bug, the image inherits the texture's planar_format that has the original fourcc; Upon querying, if planar_format is set, return the saved fourcc; Otherwise fall back to the old way. v3: add a bug description and "cc mesa-stable" tag (Jason) remove redundant null pointer check (Tapani) squash 2 patches into one (James) v2: fall back to intel_lookup_fourcc() when planar_format is NULL (Dongwon & Matt Roper) Cc: [email protected] Signed-off-by: Xiong, James <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* nir: Fix a typo in src/compiler/Makefile.nir.amBastien Orivel2018-04-091-1/+1
| | | | | | | | Since 31d91f019b58ca362c05db1fd0c75fedd169cd7b, the makefile tries to find the file SConstript.spirv instead of SConscript.spirv which breaks the make dist command. Reviewed-by: Brian Paul <[email protected]>
* radv: fix prefetching of vertex shader and VBOs on SISamuel Pitoiset2018-04-091-1/+1
| | | | | | | | Forgot one check... Too many mistakes for a simple change. Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders on CIK and older chips") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement VK_AMD_shader_core_propertiesSamuel Pitoiset2018-04-092-0/+41
| | | | | | | Simple extension that only returns information for AMD hw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add RADV_NUM_PHYSICAL_VGPRS constantSamuel Pitoiset2018-04-092-2/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_num_physical_sgprs() helperSamuel Pitoiset2018-04-092-11/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Update the XML and headers to 1.1.72Samuel Pitoiset2018-04-093-51/+445
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* docs: properly escape charactersAndres Gomez2018-04-091-1/+1
| | | | Signed-off-by: Andres Gomez <[email protected]>
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