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* radv: add has_clear_state and enable it on CIK+ onlySamuel Pitoiset2017-10-122-1/+6
| | | | | | | | This will allow us to emit the CLEAR_STATE packet instead of a bunch of useless packets when doing CS initialization. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: do not set registers for merged ES-GS on GFX9Samuel Pitoiset2017-10-121-2/+5
| | | | | | | Based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: move the raster config emission in si_set_raster_config()Samuel Pitoiset2017-10-121-53/+60
| | | | | | | Similar to RadeonSI, also only call this function for <= VI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
| | | | | | Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8 Reviewed-by: Marek Olšák <[email protected]>
* gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formatsNicolai Hähnle2017-10-121-0/+13
| | | | | | | This is a left-over from my version of adding the new format after rebasing on Eric's version. Reviewed-by: Marek Olšák <[email protected]>
* include/drm-uapi: clarify when headers can be updated.Dave Airlie2017-10-121-0/+3
| | | | | | | | Clarify when headers can be updated here. Reviewed-by: Gurchetan Singh<[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: remove duplicate line of codeTimothy Arceri2017-10-121-1/+0
| | | | | | | The same line of code is a few lines above. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: make use of on-disk cacheTimothy Arceri2017-10-121-2/+25
| | | | | | | | If the app provided in-memory pipeline cache doesn't yet contain what we are looking for, or it doesn't provide one at all then we fallback to the on-disk cache. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create on-disk shader cacheTimothy Arceri2017-10-123-0/+34
| | | | | | | This is the drivers on-disk cache intended to be used as a fallback as opposed to the pipeline cache provided by apps. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove duplicate debug_flags fieldTimothy Arceri2017-10-129-17/+14
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: intel: use anv_image's computed size for importing a BOLionel Landwerlin2017-10-111-11/+15
| | | | | | | | Rather than relying on size = stride * height, we can rely on anv_image's total size. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Daniel Stone <[email protected]>
* anv: bo_cache: allow importing a BO larger than neededLionel Landwerlin2017-10-111-1/+1
| | | | | | | | | | | It's not a problem if a BO has been allocated larger than we need it to be. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102940 Fixes: 818b857914 ("anv: Use the BO cache for DeviceMemory allocations") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Cc: [email protected]
* st/glsl_to_tgsi: the second destination doesn't support relative addressingNicolai Hähnle2017-10-111-5/+2
| | | | | | | | It's not used -- DFRACEXP gets array indexes of its exponent out-parameter lowered earlier -- and it wouldn't have worked correctly anyway when both dst and dst1 use relative addressing. Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: fix DFRACEXP with only one destinationNicolai Hähnle2017-10-111-15/+23
| | | | | | | | Replace the undefined destination by a new temporary register. Cleanup merge_two_dsts while we're at it. Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: fix indirect access to 64-bit integerNicolai Hähnle2017-10-111-1/+1
| | | | | | | | | | | | Make sure we actually allocate two adjacent TGSI temporaries. The current code fails e.g. when an arithmetic operation has two operands with indirect accesses. I will send out a new piglit test (arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test) Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: don't assign prog->ShadowSamplersNicolai Hähnle2017-10-112-5/+0
| | | | | | | | It's not used, and the assignment for the TGSI case was incorrect for sampler arrays. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with ↵Nicolai Hähnle2017-10-118-17/+63
| | | | | | | | | | | | | | texelFetch*() See the comment for the relevant spec quote. Fixes dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch v2: note the interaction between ARB_bindless_texture and EXT_texture_sRGB_decode as a TODO Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: store state that affects sampler views per contextNicolai Hähnle2017-10-114-41/+44
| | | | | | | | | | | | | This fixes sequences like: 1. Context 1 samples from texture with sRGB decode enabled 2. Context 2 samples from texture with sRGB decode disabled 3. Context 1 samples from texture with sRGB decode disabled Previously, step 3 would see the prev_sRGBDecode value from context 2 and would incorrectly use the old sampler view with sRGB decode enabled. Reviewed-by: Marek Olšák <[email protected]>
* swr: simd16 shaders work in progressTim Rowley2017-10-113-2/+21
| | | | | | | | Start building vertex shaders as simd16. Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment. Reviewed-by: Bruce Cherniak <[email protected]>
* gallium: allow 512-bit vectorsTim Rowley2017-10-112-9/+9
| | | | | | | | | Increase the max allowed vector size from 256 to 512. No piglit llvmpipe regressions running on avx2. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.Kenneth Graunke2017-10-111-1/+1
| | | | | | | | | | The original implementation allocated a new BO here, but we decided to switch to intel_upload_space, which returns a reference to the current upload BO. We accidentally kept the brw_bo_alloc, even though it's no longer necessary - intel_upload_space will immediately unreference it, causing us to allocate and immediately free a buffer. Reviewed-by: Plamena Manolova <[email protected]>
* i965: Allow mapped VBOs during drawing in non-debug contexts.Kenneth Graunke2017-10-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | Section 6.3.2 of the GL 4.5 spec says: "Any GL command which attempts to read from, write to, or change the state of a buffer object may generate an INVALID_OPERATION error if all or part of the buffer object is mapped ... However, only commands which explicitly describe this error are required to do so. If an error is not generated, such commands will have undefined results and may result in GL interruption or termination." Setting this flag allows us to skip walking over the buffer bindings for every enabled vertex attribute (_mesa_all_buffers_are_unmapped). Improves performance in GFXBench4's gl_driver2_off microbenchmark by 3.05797% +/- 0.709031% (n=33) on Apollolake. This breaks KHR-*.draw_elements_base_vertex_tests.invalid_mapped_bos, but that test is invalid and has been removed from the upstream CTS. Reviewed-by: Eric Anholt <[email protected]>
* meson: fix glx testDylan Baker2017-10-111-0/+1
| | | | | | | | That requires a generated header that was rolled into a loop. fixes: a47c525f3281a27 ("meson: build glx") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
| | | | | | | | | | | | | | | | Previously buffer offsets were passed in explicitly as an offset, which had to be added to the resource address. Now they are passed in via an increased 'start' parameter. As a result, we were double-adding the start offset in this kind of situation. This condition was triggered by piglit's draw-elements test which has a requisite glMultiDrawElements in combination with a small enough number of vertices to go through the immediate push path. Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer") Reported-by: Karol Herbst <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* i965: Make brw_update_texture_surface static.Kenneth Graunke2017-10-112-5/+1
| | | | Trivial. It's not used in other files.
* Android: fix build break from r600/radeon splitRob Herring2017-10-103-2/+6
| | | | | | | | | | | | | | | Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the Android build: external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found ^~~~~~~~~~~~~~~~~~~~~~~~ Update the Android makefiles so that drivers/radeon is only built when radeonsi (and therefore LLVM) is enabled. Fixes: 06bfb2d28f7a (r600: fork and import gallium/radeon) Acked-by: Marek Olšák <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* Android: move libraries to /vendorRob Herring2017-10-101-2/+3
| | | | | | | | | | | As part of Treble project in Android O, all the device specific files have to be located in a separate vendor partition. This is done by setting LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not break existing platforms without a vendor partition as it will just move files to /system/vendor. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARB_enhanced_layouts allows multiple output variables to share the same location - and these variables may not have the same sizes. For example, consider these output variables: // consume X/Y/Z components of 6 vectors layout(location = 0) out vec3 a[6]; // consumes W component of the first vector layout(location = 0, component = 3) out float b; Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24 components worth of space (vec3 padded out to a vec4, 4 * 6 = 24). But looking at the second declaration, we would think that VARYING_SLOT_VAR0 needs only 4 components of space (a single float padded out to a vec4). nir_setup_outputs() only considered the space requirements of the first declaration it happened to see, so if 'float b' came first, it would underallocate the output register space, causing brw_fs_validator.cpp to assert fail about inst->dst.offset exceeding the register size. Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/ vs-to-fs-array-interleave-single-location.shader_test. Thanks to Tim Arceri for finding this bug and writing a test! Reviewed-by: Timothy Arceri <[email protected]>
* nir: bump loop unroll limit to 96.Dave Airlie2017-10-111-1/+3
| | | | | | | | | | | With the ssao demo from Vulkan demos: radv/rx480: 440->440fps anv/haswell: 24->34 fps The demo does a 0->32 loop across a ubo with 32 members. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv: fix assert in wsi image code.Dave Airlie2017-10-111-1/+1
| | | | | | | | | | This assert was firing just running demos. Jason said it should be this. Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image) Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st: fix atomic buffer sizing to align with ssbo.Dave Airlie2017-10-111-0/+6
| | | | | | | | This respects the size from the range setting like ssbo. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/bufferobj: consolidate some buffer binding code.Dave Airlie2017-10-111-42/+35
| | | | | | | | | These paths are again 90% the same, consolidate them into one. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.Dave Airlie2017-10-111-102/+47
| | | | | | | | | These are 90% the same code, consolidate them into a couple of common codepaths. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: rename various buffer bindings to one struct.Dave Airlie2017-10-117-45/+20
| | | | | | | | One binding to bind them all, these are all the same thing. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: align atomic buffer handling code with ubo/ssbo (v1.1)Dave Airlie2017-10-112-44/+92
| | | | | | | | | | | | | | this adds automatic size support to the atomic buffer code, but also realigns the code to act like the ubo/ssbo code. v1.1: add missing blank lines. reindent one block properly. check for NullBufferObj. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Don't try to decode types for non-existent src1.Kenneth Graunke2017-10-101-1/+2
| | | | | | | | | | | | | | KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits this validation path. MOVs don't have a src1 file, but calling brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE and the hw_type being something invalid for immediates. To work around this, just pretend src1 is src0 if there isn't a src1. Fixes: 2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special Requirements for Handling Double Precision Data Types") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680 Reviewed-by: Alejandro Piñeiro <[email protected]>
* main/format: skip format conversion if src and dst format are equalKarol Herbst2017-10-101-0/+14
| | | | | | | | | | | Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965. v2: (by Kenneth Graunke) Rewrite patch according to Jason Ekstrand's review feedback. This makes it handle differing strides, which i965 needed. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Make _mesa_get_format_bytes handle array formats.Jason Ekstrand2017-10-101-0/+5
| | | | | | This is easier than making callers handle a bunch of special cases. Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
| | | | | | | | Older kernels fail the va_op with this flag set. If the kernel supports GFX9 usefully, it will also support this flag. Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space" Reviewed-by: Dave Airlie <[email protected]>
* i965: Disable auxiliary buffers when there are self-dependencies.Kenneth Graunke2017-10-103-25/+37
| | | | | | | | | | | | | | | | | | | Jason and I investigated several OpenGL CTS failures where the tests bind the same texture for rendering and texturing, at the same time. This has defined results as long as the reads happen before writes, or the regions are non-overlapping. Normally, this just works out. However, CCS can cause problems. If the shader is reading one set of pixels, and writing to different pixels that are adjacent, they may end up being covered by the same CCS block. So rendering may be writing a CCS block, while the sampler is trying to read it. Corruption ensues. Disabling CCS is unfortunate, but safe. Fixes several KHR-GL45.texture_barrier.* subtests. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
| | | | | | | Only r600 target used now for compute IR. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | | | | | | | So it appears the Vulkan SPIR-V fma opcode can be equivalent to a mad operation, and the fma hw opcode on AMD hw is issued like a double opcode so is slower. Also the radeonsi stack does this. This appears to improve performance on a number of games from Feral, and thanks to Feral for noticing the problem. I'm reposting this one as Marek indicated he thinks this is what we should be doing on AMD hw. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
| | | | | | Signed-off-by: Alex Smith <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
| | | | | Like vc4, we have the alpha in the low bit. Fixes a bunch of piglit texwrap failures.
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
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* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-102-4/+45
| | | | Fixes arb_color_buffer_float-clear
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
| | | | Fixes fbo-mrt-alphatest.
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
| | | | | I cut the line out to move it up to the top, when putting "0" in the switch made the compiler complain that that wasn't a valid enum.
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