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* freedreno/ir3: move const_state back to variantRob Clark2020-06-197-40/+54
* freedreno/ir3: un-embed const_stateRob Clark2020-06-198-10/+21
* freedreno/ir3: move num_reserved_user_consts out of const_stateRob Clark2020-06-193-3/+3
* freedreno/ir3: convert over to rallocRob Clark2020-06-193-26/+8
* freedreno/ir3: pass variant to ir3_create()Rob Clark2020-06-194-6/+8
* ir3: Split out variant-specific lowering and optimizationsConnor Abbott2020-06-195-96/+109
* freedreno/ir3: constify shader keyRob Clark2020-06-192-5/+5
* freedreno/ir3: drop shader->num_ubosRob Clark2020-06-194-17/+15
* freedreno/ir3: move ubo_state into const_stateRob Clark2020-06-199-28/+27
* freedreno/a6xx: defer userconst cmdstream size calculationRob Clark2020-06-193-25/+25
* freedreno/ir3: add accessor for const_stateRob Clark2020-06-1910-28/+39
* freedreno/ir3: refactor out helper to compile shader from asmRob Clark2020-06-198-48/+127
* st/mesa: make texture views inherit compressed_data storagePierre-Eric Pelloux-Prayer2020-06-192-6/+27
* ac/llvm: load 1 byte at a time if unaligned on gfx10Pierre-Eric Pelloux-Prayer2020-06-191-1/+1
* r600/sfn: Handle memory_barrierGert Wollny2020-06-191-0/+1
* r600/sfn: Take SSBO buffer ID offset into accountGert Wollny2020-06-194-8/+35
* r600/sfn: Add support for reading cube image array dim.Gert Wollny2020-06-193-15/+40
* r600/sfn: Add support for image_sizeGert Wollny2020-06-192-0/+24
* r600/sfn: Add imageio supportGert Wollny2020-06-193-47/+325
* r600/sfn: lower image derefsGert Wollny2020-06-192-1/+1
* radv: require LLVM 11+ for GFX 10.3 if not using ACOSamuel Pitoiset2020-06-191-0/+6
* radv: add support for Sienna CichlidSamuel Pitoiset2020-06-195-10/+45
* aco: replace == GFX10 with >= GFX10 where it's neededSamuel Pitoiset2020-06-193-7/+7
* radv: replace == GFX10 with >= GFX10 where it's neededSamuel Pitoiset2020-06-192-3/+3
* intel/tools: Add assembler tests for the cr0 registerMatt Turner2020-06-196-0/+70
* intel/tools: Disallow control subregisters > 3Matt Turner2020-06-191-1/+1
* intel/tools: Require explicit regions/types for special regsMatt Turner2020-06-191-28/+10
* intel/tools: Drop srctype from ipregMatt Turner2020-06-191-1/+1
* intel/tools: Remove unnecessary reg number checkingMatt Turner2020-06-192-10/+1
* turnip: move enum translation functions to a common headerJonathan Marek2020-06-187-371/+247
* aco: use the same regclass as the definition for undef phi operandsRhys Perry2020-06-181-3/+3
* aco: fix edge check with sub-dword temporariesRhys Perry2020-06-182-5/+9
* mesa/main: fix inverted conditionErik Faye-Lund2020-06-181-1/+1
* nv50/ir/nir: remove image uniform hackKarol Herbst2020-06-181-11/+1
* nv50/ir/nir: handle image atomic inc and decKarol Herbst2020-06-181-0/+18
* nv50/ir/nir: move away from image_deref intrinsicsKarol Herbst2020-06-182-216/+58
* nir/lower_images: handle dec and incKarol Herbst2020-06-182-0/+4
* nir/lower_images: fix for array of arraysKarol Herbst2020-06-181-2/+9
* st/mesa: lower images when neededKarol Herbst2020-06-181-0/+3
* aco: shrink mad_infoRhys Perry2020-06-181-1/+1
* aco: make ssa_info::label 64-bitRhys Perry2020-06-181-17/+20
* aco: shrink ssa_infoRhys Perry2020-06-181-1/+1
* radeon/vcn: bump vcn3.0 encode major version to 1Boyuan Zhang2020-06-181-1/+18
* radeon/vcn/enc: Re-write PPS encoding for HEVCBoyuan Zhang2020-06-181-0/+65
* radeon/vcn: add vcn 3.0 encode supportThong Thai2020-06-185-3/+145
* radeon/vcn/dec: add db_aligned_height to message bufferLeo Liu2020-06-181-0/+4
* radeon/vcn: add Sienna to use internal register offsetLeo Liu2020-06-181-13/+25
* radeon/vcn: reset the decode flags from message bufferLeo Liu2020-06-181-1/+1
* aco: fix WQM handling in nested loopsDaniel Schürmann2020-06-181-1/+4
* st/mesa: account for "loose", per-mipmap level textures in CopyImageSubDataDanylo Piliaiev2020-06-181-2/+4
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