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* anv: use a query filled by the perf codeLionel Landwerlin2020-05-201-6/+1
| | | | | | | | | We're about to use the offset fields from the query object. We can't just use a made up object. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: report whether the platform supportedLionel Landwerlin2020-05-202-0/+9
| | | | | | Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: add counter category to generated codeLionel Landwerlin2020-05-202-0/+2
| | | | | | Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: add helper to compute metrics from countersLionel Landwerlin2020-05-202-0/+34
| | | | | | | | The produced array tells use what metric to enable for a given pass. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: emit counter units in generated codeLionel Landwerlin2020-05-202-0/+39
| | | | | | | | We'll use this coming extension. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: compute number of passes for a set of countersLionel Landwerlin2020-05-202-0/+58
| | | | | | | | | We want to compute the number of passes required to gather performance data about a set of counters. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: create a unique list of countersLionel Landwerlin2020-05-204-2/+65
| | | | | | | | | | | | | | For a future extension we want to be able to list the counters. Our existing sets counters might contain the same counters multiple times. This is a side effect of the fixed OA counters in the HW. We track thoses with a mask so that we know when a counter is available from multiple metrics. v2: Use BITFIELD64_BIT() (Jason) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: update generated code to ralloc all dataLionel Landwerlin2020-05-201-45/+29
| | | | | | | | | | Previously counter descriptions as well register values were written in global static variables. This isn't really thread safe so instead ralloc all the data back under the gen_perf_config object. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: store the appropriate OA formats in queriesLionel Landwerlin2020-05-201-7/+13
| | | | | | Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/perf: make pipeline statistic query loading optionalLionel Landwerlin2020-05-206-8/+14
| | | | | | | | | On Vulkan most of those are already covered by standard queries so add the ability to skip them. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/genxml: add PIPE_CONTROL command cache invalidate bitLionel Landwerlin2020-05-202-0/+2
| | | | | | | | | This new bit invalidates the cache/prefetch of commands in the command streamer. This will be useful for self modifying batches. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* anv: add a new execution mode for secondary command buffersLionel Landwerlin2020-05-202-5/+68
| | | | | | | | | | | | | | | | | | | | | | This change adds a call/return execution mode for secondary command buffer rather than the existing copy into the primary batch mode. v2: Rework convention to avoid burning an ALU register (Jason) v3: Use anv_address_add() (Jason) v4: Move command emissions to anv_batch_chain.c (Jason) v5: Also move last MI_BBS emission in secondary command buffer to anv_batch_chain.c (Jason) v6: Fix end secondary command buffer end (Jason) v7: Refactor anv_batch_address() to remove additional emit functions Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* anv: don't reserve a particular register for draw countLionel Landwerlin2020-05-202-40/+46
| | | | | | | | | | By using the same mi_builder throughout the draw call, we can just allocate a register from the mi_builder and unref it when we're done. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/mi-builder: add framework for self modifying batchesLionel Landwerlin2020-05-201-0/+69
| | | | | | | | | | | | v2: Use Jason's idea to store addresses to modify v3: Add ALU flushes (Jason) v4: Remove ALU flush from gen_mi_self_mod_barrier() (Jason) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMMLionel Landwerlin2020-05-201-8/+12
| | | | | | | | | | | | | | | | | | | | | This instruction has a group with the same name than another field above : <field name="Data DWord" start="64" end="95" type="uint"/> <group count="0" start="96" size="64"> <field name="Register Offset" start="2" end="22" type="offset"/> <field name="Data DWord" start="32" end="63" type="uint"/> </group> The script was replacing the offset of the field first with the second one in the group. This change ignore anything a group within an instruction. v2: Drop unused variable (Rafael) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* gitlab: Ask about reproduction rate in the issue templateDenys2020-05-201-1/+1
| | | | | Reviewed-by: <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5055>
* nir: Add const to nir_intrinsic_src_componentsJason Ekstrand2020-05-191-1/+1
| | | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5108>
* pan/mdg: Apply outmodsAlyssa Rosenzweig2020-05-191-0/+39
| | | | | Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Use helpers for branch/discard inversionAlyssa Rosenzweig2020-05-191-2/+18
| | | | | | | Doesn't come up on glmark but would covered by the old passes. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Remove invert optimizationsAlyssa Rosenzweig2020-05-197-462/+1
| | | | | | | Unused since last commit. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Treat inot as a modifierAlyssa Rosenzweig2020-05-195-8/+105
| | | | | | | | With this, we may remove all invert passes and simply look at the src modifier on NIR->MIR and fixup at pack time. No shader-db changes. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Apply abs/neg modifiersAlyssa Rosenzweig2020-05-191-0/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Ingest fsat_signed/fclamp_posAlyssa Rosenzweig2020-05-192-0/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Prepare for modifier helpersAlyssa Rosenzweig2020-05-192-87/+75
| | | | | | | | | We have to restructure to ensure NIR->MIR does not mutate the NIR and to allow passing around dest/outmods for the new helpers. If NIR->MIR were better designed this would be easier. Sigh. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Drop nir_lower_to_source_modsAlyssa Rosenzweig2020-05-191-5/+0
| | | | | | | shader-db regressions fixed shortly. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* pan/mdg: Remove .pos propagation passAlyssa Rosenzweig2020-05-191-90/+0
| | | | | | | | Will be replaced later in the series. shader-db regressions but those fixed momentarily. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* panfrost: Add modifier detection helpersAlyssa Rosenzweig2020-05-194-0/+134
| | | | | | | | | | With the goal of removing modifiers from NIR, these helpers let us detect modifier patterns without mutating the underlying NIR. These were intended for upstream, but due to various issues are being (temporarily) vendored. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* nir: Add fclamp_pos opcodeAlyssa Rosenzweig2020-05-191-0/+1
| | | | | | | | | Corresponds to the .pos modifier on all Mali GPUs (lima and panfrost). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* nir: Add fsat_signed opcodeAlyssa Rosenzweig2020-05-191-0/+1
| | | | | | | | | Exists on later Mali. Equivalent to clamp(x, -1.0, 1.0) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
* tu: Support VK_FORMAT_FEATURE_BLIT_SRC_BIT for texture-only formatsConnor Abbott2020-05-191-2/+2
| | | | | | | It turns out this is required for compressed formats, and we might as well enable it for the one other texture-only format too. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
* tu: Fix buffer compressed pitch calculation with unaligned sizesConnor Abbott2020-05-191-13/+18
| | | | | | | | | | | | | | We can just set the extent and not bufferRowLength/bufferImageHeight, and the extent may not be a multiple of the block size if it covers the entire image. In this case we have to first divide to get the width/height in terms of blocks, and then multiply by the block size to get the buffer's pitch and layer size. Multiplying and dividing instead won't get the correct result when the extent covers the entire image and isn't a multiple of the block size. This also makes the code easier to follow because we don't calculate a pitch in non-sensical units (bytes times the block width) as an intermediate step. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
* tu: Fall back to 3d blit path for BC1_RGB_* formatsConnor Abbott2020-05-191-1/+11
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
* tu: Always initialize image_view fields for blit sourcesConnor Abbott2020-05-191-26/+28
| | | | | | | | | | Previously we only supported BLIT_SRC_BIT and BLIT_DEST_BIT together, so we didn't have to worry about initializing blit-related fields for texture-only formats, but it turns out that 2d blits work out just fine with these formats and we'll need to enable BLIT_SRC_BIT for texture-only formats due to a Vulkan requirement on compressed formats. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
* nir: Add a store_reg helper and use the builder in phis_to_regsJason Ekstrand2020-05-192-21/+25
| | | | | | Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
* nir: Add a new helper for iterating phi sources leaving a blockJason Ekstrand2020-05-193-15/+30
| | | | | | | | | This takes the same callback as nir_foreach_src except it walks all phi sources which leave a given block. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
* nir/clone: Re-use clone_alu for nir_alu_instr_cloneJason Ekstrand2020-05-191-21/+17
| | | | | | | | | | | | All it takes are a couple small tweaks to the clone infrastructure to allow us to use it without any remap table at all. This reduces code duplication and the chances for bugs that come with it. In particular, the hand-rolled nir_alu_instr_clone didn't preserve no_[un]signed_wrap, or source/destination modifiers. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
* radv/winsys: Finish mapping for sparse residency.Bas Nieuwenhuizen2020-05-191-21/+42
| | | | | | | | This adds the part that disables pagefaults when unbacked sparse textures get accessed. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5079>
* intel/drm-shim: Return correct values for I915_PARAM_HAS_ALIASING_PPGTTIan Romanick2020-05-191-1/+6
| | | | | | | | | | | | | | | | It sure looks like it should be a Boolean value, but it's not. The values that we really want for later platforms are either 2 or 3. The old intel_stub.c in shader-db just always returns 3 (I915_GEM_PPGTT_FULL). This returns the same set of values per platform that kernel 5.6.13 would. When using the shim for ICL with i965 driver, this fixes: i965 requires softpin (Kernel 4.5) on Gen10+. Fixes: 0f4f1d70bfe ("intel: add stub_gpu tool") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
* intel/drm-shim: Add noop ioctl handler for set_tilingIan Romanick2020-05-191-0/+1
| | | | | | | | | | When using the shim for HSW and earlier, this fixes: DRM_SHIM: unhandled driver DRM ioctl 33 (0xc0106461) Fixes: 0f4f1d70bfe ("intel: add stub_gpu tool") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
* radv: Expose VK_EXT_pipeline_creation_cache_control.Bas Nieuwenhuizen2020-05-193-0/+8
| | | | | | Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2972 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
* radv: Support VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT.Bas Nieuwenhuizen2020-05-192-18/+39
| | | | | Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
* radv: Support VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT.Bas Nieuwenhuizen2020-05-191-0/+12
| | | | | Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
* radv: Support VK_PIPELINE_COMPILE_REQUIRED_EXT.Bas Nieuwenhuizen2020-05-193-12/+32
| | | | | Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
* panfrost: Enable AFBC for Z24X8Alyssa Rosenzweig2020-05-191-5/+2
| | | | | Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
* panfrost: Fix Z24 vs Z32 mixupAlyssa Rosenzweig2020-05-195-13/+6
| | | | | | | | We don't actually support Z32_UNORM; the format we've been using as such is in fact Z24X8 / Z24S8. Fix that and drop Z32_UNORM. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
* panfrost: Switch formats to tableAlyssa Rosenzweig2020-05-197-269/+288
| | | | | | | | | | | | | Rather than heuristically guessing what PIPE formats correspond to what in the hardware, hardcode a table. This is more verbose, but a lot more obvious -- the previous format support code was a source of endless silent bugs. v2: Don't report RGB233 (icecream95). Allow RGB5 for texturing (icecream95). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
* pan/mfbd: Add format codes for PIPE_FORMAT_B5G5R5A1_UNORMAlyssa Rosenzweig2020-05-191-1/+7
| | | | | Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
* nir/opt_if: use nir_src_as_bool in opt_peel_loop_initial_if helperRhys Perry2020-05-191-12/+10
| | | | | | Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4757>
* nir/opt_if: run opt_peel_loop_initial_if after all other optimizationsRhys Perry2020-05-197-17/+44
| | | | | | | | | | | | | Fixes dEQP-VK.graphicsfuzz.loops-ifs-continues-call with RADV. opt_if_loop_terminator can cause this optimization or opt_if_simplification to be run on the non-SSA code. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Fixes: 52c8bc0130a ('nir: make opt_if_loop_terminator() less strict') Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2943 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4757>
* nir: Add documentation for each jump instruction typeJason Ekstrand2020-05-191-0/+18
| | | | | Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5101>