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* st/mesa: remove unused st_xxx_program::sha1Marek Olšák2019-10-171-6/+0
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: remove st_vp_variant_key in favor of st_common_variant_keyMarek Olšák2019-10-173-25/+8
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: remove num_tgsi_tokens from st_xx_programMarek Olšák2019-10-173-30/+16
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: rename basic -> common for st_common_programMarek Olšák2019-10-175-30/+30
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: rename st_xxx_program::tgsi to stateMarek Olšák2019-10-176-97/+97
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: lower doubles for NIR after linkingMarek Olšák2019-10-171-20/+17
| | | | | | | This allows dropping 1 call to st_nir_opts, because shaders are always optimized after linking. Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: call st_nir_opts for linked shaders only onceMarek Olšák2019-10-171-1/+12
| | | | | | | | | | | | | | | | | | The removed st_nir_opts calls are mostly redundant. There is an improvement with shader-db on radeonsi: Before: real 1m54.047s user 28m37.857s sys 0m7.573s After: real 1m52.012s user 28m3.412s sys 0m7.808s Reviewed-by: Timothy Arceri <[email protected]>
* intel/vec4: Don't try both sources as immediates for DPHIan Romanick2019-10-171-1/+1
| | | | | | | | | | DPH isn't actually commutative, so this doesn't work. If the immediate in src0 would be a VF candidate, we could do better. *shrug* No shader-db changes on any Intel platform. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Fixes: b04beaf41d2 ("intel/vec4: Try both sources as candidates for being immediates")
* nir/search: Fix possible NULL dereference in is_fsignIan Romanick2019-10-171-1/+1
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Fixes: 09705747d72 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
* iris: Let isl decide the supported tiling in more situationsJordan Justen2019-10-171-15/+0
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Suggested-by: Nanley Chery <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Add gen12 depth/stencil surface alignmentsJordan Justen2019-10-175-2/+123
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Select Y-tiling for stencil on gen12Jason Ekstrand2019-10-171-4/+7
| | | | | | | | | | Rework: * Disallow linear 1D stencil buffers (Nanley) * Force Y for gen12 stencil rather than ~W (Nanley) Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-172-1/+3
| | | | | | It's no longer supported by the hardware Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-172-6/+52
| | | | | | | | | Rework: * NULL stencil buffer path (Jason) * genxml fixes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-172-10/+14
| | | | | | | | | Reworks: * Fix 3DSTATE_DEPTH_BUFFER "Surface Format" end in xml (Jason) * Remove WM_HZ_OP changes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-172-12/+19
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* mesa: Refactor the entirety of _mesa_format_matches_format_and_type().Eric Anholt2019-10-176-642/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | This function was difficult to implement for new formats due to the combination of endianness and swapbytes support. Since it's mostly used for fast paths, bugs in it were often missed during testing. Just reimplement it on top of the recent _mesa_format_from_format_and_type() which can give us a canonical MESA_FORMAT for a format and type enum (while respecting endianness). Fixes: - R4G4B4A4_UNORM, B4G4R4_UINT, R4G4B4A4_UINT incorrectly matched with swapBytes (you can't just reverse the channels if the channels aren't bytes) - A4R4G4B4_UNORM and A4R4G4B4_UINT missing BGRA/4444_REV matches - failing to match RGB/BGR unorm8 array formats on BE - 2101010 formats incorrectly matching with swapBytes set. - UINT/SINT byte formats failed to match with swapBytes set. This deletes the part of tests/mesa_formats.cpp that called _mesa_format_matches_format_and_type() to make sure it didn't assertion fail, as it now would assertion fail due to the fact that we were passing an invalid format (GL_RG) for most types. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add support for array formats of depth and stencil.Eric Anholt2019-10-176-8/+83
| | | | | | | | | | | In desktop GL, you can specify things like GL_DEPTH_COMPONENT/GL_BYTE as a ReadPixels format, and we need to be able to represent that to see if we have proper MESA_FORMATs for them. That's exactly what the mesa_array_format enum is for. v2: Drop _mesa from static fn. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add format/type matching for DEPTH/UINT_24_8.Eric Anholt2019-10-171-0/+2
| | | | | | | | We had missed this case where GLES3 allows glReadPixels(DEPTH, UINT_24_8), and just got lucky by the readpixels path never asking for the matching format from this function. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Fix depth/stencil ordering in _mesa_format_from_format_and_type().Eric Anholt2019-10-171-1/+1
| | | | | | | | | | The GL spec says the 24-bit component is in the high bits, and format_unpack.c looks at the high 24 bits in the S8Z24 case, not Z24SS8. Avoids a regression in the next commit. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add debug info to _mesa_format_from_format_and_type() error path.Eric Anholt2019-10-171-0/+4
| | | | | | | The unreachable() that follows isn't very useful for debug, and by adding this here we get a nice description of the failure in debug builds. Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/a6xx: Turn on geometry shadersKristian H. Kristensen2019-10-172-3/+15
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ci: Add failing tests to skip listKristian H. Kristensen2019-10-171-0/+4
| | | | | | Some queries are still failing and layered rending needs more work. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Implement PIPE_QUERY_PRIMITIVES_GENERATED for GSKristian H. Kristensen2019-10-173-0/+68
| | | | | | | When we don't have streamout enabled, we have to read this register to get the number of primitives emitted. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/blitter: Save GS stateKristian H. Kristensen2019-10-171-0/+1
| | | | | | We have GS state now. Signed-off-by: Kristian H. Kristensen <[email protected]>
* st/mesa: Also enable GS when ESSLVersion > 320Kristian H. Kristensen2019-10-171-1/+1
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Support layered render targetsKristian H. Kristensen2019-10-174-4/+32
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Emit program state for GSKristian H. Kristensen2019-10-173-26/+148
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: End VS with CHMASK and CHSH in GS pipelinesKristian H. Kristensen2019-10-171-1/+18
| | | | | | | | | | | When used in a GS pipeline, the VS doesn't end with the END instruction. Instead it chains to the GS, which continues running with the same register allocation. The intended use cases seems to be that you can compile a regular VS (ie outputs in registers and ending with END) but then tack on link-time generated code past the END to write the outputs using STLW, in case the VS is used with GS. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Start GS with (ss) and (sy)Kristian H. Kristensen2019-10-171-0/+13
| | | | | | | We don't know what kind of loads we might have to wait on when coming in from chsh in the VS so set both sync flags. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Pre-color GS header and primitive IDKristian H. Kristensen2019-10-171-0/+9
| | | | | | | | | These sysvals have to be unclobbered by VS and in the same registers in both VS and GS, since the chsh from VS to GS doesn't reload the values. We use the pre-color argument to ir3_ra() to always place these values in r0.x and r0.y. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Setup ir3 inputs and outputs for GSKristian H. Kristensen2019-10-171-3/+64
| | | | | | | | | | | | Inputs are the GS header, which contains vertex ID, local primitive ID and thread ID as well as primitive ID. The setup is a little different from other sysvals, since we always have to receive them in the VS so that it can pass them on into the GS. The vertex flag outputs from GS is set up as a proper nir output in the lowering pass and doesn't need special handling here. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Implement primitive layout intrinsicsKristian H. Kristensen2019-10-178-4/+113
| | | | | | | | This implements the load_vs_primitive_stride_ir3, load_vs_vertex_stride_ir3 and load_primitive_location_ir3 intrinsics, used for getting the primitive layout strides and locations. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Implement lowering passes for VS and GSKristian H. Kristensen2019-10-1713-2/+517
| | | | | | | | This introduces two new lowering passes. One to lower VS to explicit outputs using STLW and one to lower GS to load input using LDLW and implement the GS specific functionality. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add has_gs flag to shader keyKristian H. Kristensen2019-10-172-5/+11
| | | | | | | Since the presence of GS changes how the VS operates we need to track that in the shader key. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Add missing adjacency primitives to tableKristian H. Kristensen2019-10-171-8/+12
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add intrinsics that map to LDLW/STLWKristian H. Kristensen2019-10-172-0/+83
| | | | | | | These intrinsics will let us do all the offset calculations in nir, which is nicer to work with and lets nir_opt_algebraic eat it all up. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add new LDLW/STLW instructionsKristian H. Kristensen2019-10-174-3/+8
| | | | | | These access memory used for passing data between geometry stages. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Extend RA with mechanism for pre-coloring registersKristian H. Kristensen2019-10-173-50/+60
| | | | | | | We'll need to pre-color certain input registers betwee VS and GS shaders. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Use third register for offset for LDL and LDLVKristian H. Kristensen2019-10-174-12/+18
| | | | | | | | Before, offset held the offset, which can be either immediate or a register. Use a third register to hold the offset so that we can use a register. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add support for CHSH and CHMASK instructionsKristian H. Kristensen2019-10-172-1/+3
| | | | | | | Just add the constructors for now and special case similar to END so we don't remove them. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Trim a few regs from fd6_emit_restore()Kristian H. Kristensen2019-10-171-20/+0
| | | | | | | We know what these do an either write them in the program stateobj or don't need to write them. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/registers: Update with GS, HS and DS registersKristian H. Kristensen2019-10-176-12/+108
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ci: Ban texsubimage2d_pbo.r16ui_2d, due to two flakes reported.Eric Anholt2019-10-171-0/+3
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* st/mesa: silence a warning in st_nir_lower_tex_src_planeMarek Olšák2019-10-171-1/+1
| | | | trivial
* gallium/u_blitter: remove an unused variableMarek Olšák2019-10-171-2/+0
| | | | trivial
* radeonsi: recreate aux_context after a GPU resetMarek Olšák2019-10-171-3/+25
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: call the reset callback if get_device_reset_status returns a failureMarek Olšák2019-10-173-20/+7
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* st/mesa: call the reset callback if glGetGraphicsResetStatus returns a failureMarek Olšák2019-10-171-12/+14
| | | | | | so that we immediately set the no-op dispatch Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* intel/fs/gen12: Add tests for scoreboard passCaio Marcelo de Oliveira Filho2019-10-172-1/+864
| | | | | | | | | | | | | Tests the combinations of cases of RAW, WAW and WAR hazards involving both inorder and outoforder instructions. Also tests that dependencies combine and propagate correctly through control flow (loops and conditionals). v2: Add an extra test illustrating that the non-logical CFG edge between then-block and else-block is being taking into account. (Curro) Reviewed-by: Francisco Jerez <[email protected]>
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