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* anv: Add a new enum to identify the pipeline typeCaio Marcelo de Oliveira Filho2020-03-123-0/+8
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* glsl/tests: Fix waiting for disk_cache_put() to finish.Eric Anholt2020-03-123-42/+23
| | | | | | | | | | | | We were wasting 4s on waiting for expected-not-to-appear files to show up on every test. Using timeouts in test code is error-prone anyway, as our shared runners may be busy on other jobs. Fixes: 50989f87e62e ("util/disk_cache: use a thread queue to write to shader cache") Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2505 Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140>
* glsl/tests: Catch mkdir errors to help explain when they happen.Eric Anholt2020-03-121-2/+14
| | | | | | | | | | | | A recent pipeline (https://gitlab.freedesktop.org/Venemo/mesa/-/jobs/1893357) failed with what looks like an intermittent error related to making files for the cache test inside of the core of the cache. Given some of the errors, it looks like maybe a mkdir failed, so log those errors earlier so we can debug what's going on next time. Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140>
* intel/fs: Combine adjacent memory barriersCaio Marcelo de Oliveira Filho2020-03-121-0/+22
| | | | | | | | | | | | | | | | This will avoid generating multiple identical fences in a row. For Gen11+ we have multiple types of fences (affecting different variable modes), but is still better to combine them in a single scoped barrier so that the translation to backend IR have the option of dispatching both fences in parallel. This will clean up redundant barriers from various dEQP-VK.memory_model.* tests. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
* nir: Add pass to combine adjacent scoped memory barriersCaio Marcelo de Oliveira Filho2020-03-124-0/+95
| | | | | | | | | | SPIR-V generates very granular barriers, however HW and backends might not necessarily take advantage of those. This pass provides a general mechanism to combine such barriers. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
* nir: Reorder nir_scopes so wider scope has larger numeric valueCaio Marcelo de Oliveira Filho2020-03-121-4/+4
| | | | | | | | Makes code comparing and combining scopes slightly more readable. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
* nir: Don't skip a bit in nir_memory_semanticsCaio Marcelo de Oliveira Filho2020-03-121-2/+2
| | | | | | | | | | There was another enum entry in the draft versions of nir_memory_semantics, but when it got dropped the entries were not updated. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
* radv: use ac_gpu_info::use_late_allocSamuel Pitoiset2020-03-121-4/+6
| | | | | | | | | Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
* radv: rewrite late alloc computationSamuel Pitoiset2020-03-121-34/+43
| | | | | | | | Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
* radv: tune primitive binning for small chipsSamuel Pitoiset2020-03-121-2/+7
| | | | | | | | Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
* radv: use better tessellation tunables on GFX9+Samuel Pitoiset2020-03-121-1/+8
| | | | | | | | Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
* radv/gfx10: cache metadata in L2 on small chipsSamuel Pitoiset2020-03-121-8/+21
| | | | | | | | Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
* intel/isl: Set DepthStencilResource based on aux usageJason Ekstrand2020-03-121-2/+30
| | | | | | | | | | | | | | | | | | | | In ISL, usage flags only carry intent and not semantic meaning. We don't have a bulletproof way in ISL to specify that an image is of depth/stencil type. The usage flags are great but blorp, for instance, loves to disrespect them. One proposed solution to this problem is to add explicit depth/stencil formats which are distinct from the corresponding color formats. Fortunately, however, empirical evidence suggests that this bit only affects the sampler's interpretation of the CCS data. Therefore, we can set the bit based off of the aux_usage which is now very specific and does carry semantic meaning. In particular, aux_usage now makes a distinction between color CCS and depth/stencil CCS which appears to be exactly what the DepthStencilResource bit is for. Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel: Require ISL_AUX_USAGE_STC_CCS for stencil CCSJason Ekstrand2020-03-123-3/+6
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCSJason Ekstrand2020-03-123-4/+17
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/blorp: Allow STC_CCS in blit sourcesJason Ekstrand2020-03-121-1/+2
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/isl: Add a separate ISL_AUX_USAGE_STC_CCSJason Ekstrand2020-03-126-4/+31
| | | | | | | | | | | | | | Stencil CCS is slightly different from color CCS. Using a color CCS resolve with stencil CCS doesn't do the right thing and you can't sample from a stencil CCS image without the DepthStencilResource bit set or you will get the wrong data. Stencil CCS also has it's own rules such as it doesn't support fast-clear and has no partial resolve. This seems to indicate that it should probably be its own isl_aux_usage. Now that adding new isl_aux_usage values is pretty cheap, let's split stencil CCS out on its own. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/isl: Require ISL_AUX_USAGE_HIZ_CCS_WT for HZ+CCS WT modeJason Ekstrand2020-03-124-20/+3
| | | | | | | | | | | | We also delete the badly named isl_surf_supports_hiz_ccs_wt. The name is misleading because it doesn't return whether or not the surface supports HiZ+CCS in write-through mode (any single-sampled HiZ+CCS capable surface does) but rather a heuristic decision about whether or not we want to enable write-through mode based on the usage flags in the isl_surf. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZJason Ekstrand2020-03-124-11/+23
| | | | | | | | | | | | | Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let ISL choose write-through based on isl_surf_supports_hiz_ccs_wt. This commit makes us choose explicitly at surface creation time whether to use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions. This is more explicit and should be more robust as it lets us choose WT mode in one place rather than trusting isl_surf_supports_hiz_ccs_wt to return the same thing every time. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/blorp: Allow HIZ_CCS_WT in copy sourcesJason Ekstrand2020-03-121-1/+2
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WTJason Ekstrand2020-03-124-9/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is distinct from ISL_AUX_USAGE_HIZ_CCS in that the HiZ surface operates in write-through mode which means that the HiZ surface is only used for depth-testing acceleration and the CCS-compressed main surface is always valid so we can texture from it. Separating full HiZ from write-through mode at the isl_aux_usage level has a couple of advantages: 1. It's more explicit. Instead of write-through mode depending on the heuristic decision in isl_surf_supports_hiz_ccs_wt, it's now something that's explicitly requested by the driver. This should be more robust than hoping isl_surf_supports_hiz_ccs_wt always returns the same thing every time. If someone (say BLORP) ever drops a usage flag on the isl_surf, there's a chance it could return a different value without us noticing leading to corruptions. 2. Because ISL_AUX_USAGE_HIZ_CCS_WT is it's own isl_aux_usage flag, we can say inside the driver that HIZ_CCS does not support sampling but HIZ_CCS_WT does. We can also pass HIZ_CCS_WT to isl_surf_fill_state and it can do some validation for us beyond what we would be able to do if we conflate HIZ_CCS_WT and CCS_E. 3. In the future, we can add new heuristics to the driver which do things such as start all depth surfaces (regardless of usage flags) off in HIZ_CCS and then do a full resolve and drop to HIZ_CCS_WT the first time it gets used by the sampler. This would potentially let us enable the faster HIZ_CCS mode even in cases where it technically comes in through the API as a texture. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/isl: Clean up some aux surface logicJason Ekstrand2020-03-121-15/+11
| | | | | | | | | | | The first check is redundant because the first thing we do in the "emit the aux surface" section is assert that we actually have an aux_surf. The second check involves an exclusion list of things which don't have aux surfaces on Gen12 but an inclusion list is much simpler because it's just "does it have MCS?". Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* ac: disable late alloc on small gfx10 chipsMarek Olšák2020-03-121-1/+2
| | | | | | | | same as PAL. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* ac: add radeon_info::use_late_alloc to control LATE_ALLOC globallyMarek Olšák2020-03-125-6/+15
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi: tune primitive binning for small chipsMarek Olšák2020-03-121-3/+9
| | | | | | | same as PAL Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi: set better tessellation tunables on gfx9 and gfx10Marek Olšák2020-03-121-1/+8
| | | | | | | same as PAL Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi/gfx10: cache metadata in L2 on small chipsMarek Olšák2020-03-121-8/+19
| | | | | | | same as PAL. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radv/sqtt: describe layout transitions with user markersSamuel Pitoiset2020-03-125-1/+126
| | | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138>
* radv/sqtt: describe begin/end subpass barriers with user markersSamuel Pitoiset2020-03-121-0/+8
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138>
* nir/algebraic: coalesce fmod loweringJuan A. Suarez Romero2020-03-121-2/+1
| | | | | | | | | | | | | As fmod for 16/32/64 bits lowering does the same, let's merge all of them in a single case. Fixes dEQP-VK.glsl.builtin.precision_double.mod.compute.* on ACO. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118>
* nir/lower_double_ops: relax lower mod()Juan A. Suarez Romero2020-03-121-9/+22
| | | | | | | | | | | | | | | | | | | | | Currently when lowering mod() we add an extra instruction so if mod(a,b) == b then 0 is returned instead of b, as mathematically mod(a,b) is in the interval [0, b). But Vulkan spec has relaxed this restriction, and allows the result to be in the interval [0, b]. For the OpenGL case, while the spec does not allow this behaviour, due the allowed precision errors we can end up having the same result, so from a practical point of view, this behaviour is allowed (see https://github.com/KhronosGroup/VK-GL-CTS/issues/51). This commit takes this in account to remove the extra instruction required to return 0 instead. Reviewed-by: Daniel Schürmann <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118>
* amd/llvm: Fix divergent descriptor indexing. (v3)Bas Nieuwenhuizen2020-03-122-105/+321
| | | | | | | | | | | | | | | | | | | | | | There are multiple LLVM passes that very much move the intrinsic using the descriptor outside of the loop, defeating the entire point of creating the loop. Defeat the optimizer by splitting the break into a separate if-statement and putting an optimization barrier on the bool in between. v2: Move from a callback based system to begin/end loop. This does not make it significantly less intrusive but is a bit nicer with all the extra struct and callback stubs. v3: Deal with non-divergent values in divergent path. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2160 Fixes: 028ce527395 "radv: Add non-uniform indexing lowering." Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4109> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4109>
* intel/fs: Fix NULL destinations on 3-source instructions again after late DCEIan Romanick2020-03-121-2/+9
| | | | | | | | | | | | | | | We considered moving this down near the call to insert_gen4_send_dependency_workarounds. By that point it's too late for a couple reasons. One, we're potentially increasing resiter pressure that may lead to anoter spill. Two, fixup_3src_null_dest tries to allocate a VGRF, but the post-register allocation shader uses physical registers. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2621 Fixes: ba2fa1ceaf4 ("intel/fs: Do cmod prop again after scheduling") Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4155> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4155>
* radv: Enable subgroup shuffle on GFX10 when ACO is used.Timur Kristóf2020-03-121-1/+2
| | | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159>
* radv: Enable lowering dynamic quad broadcasts.Timur Kristóf2020-03-121-0/+3
| | | | | | | | | | | | | | | This will lower dynamic quad broadcasts into something that both LLVM and ACO can understand. On hardware which supports shuffles, they are lowered to shuffle, on older hardware (GFX6-7) they will get lowered to constant quad broadcasts. Fixes dEQP-VK.subgroups.quad.*.subgroupquadbroadcast_nonconst_* Cc: [email protected] Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147>
* nir: Add ability to lower non-const quad broadcasts to const ones.Timur Kristóf2020-03-122-1/+42
| | | | | | | | | | | | Some hardware doesn't support subgroup shuffle, and on such hardware it makes no sense to lower quad broadcasts to shuffle. Instead, let's lower them to four const quad broadcasts, paired with bcsel instructions. Cc: [email protected] Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147>
* gen_release_notes: resolve ambiguity by renaming `version` to ↵Eric Engestrom2020-03-121-10/+10
| | | | | | | | | `previous_version` and `next_version` to `this_version` Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113>
* gen_release_notes: fix version in "you should wait" messageEric Engestrom2020-03-121-1/+1
| | | | | | | Fixes: 86079447da1e00d49db0 ("scripts: Add a gen_release_notes.py script") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113>
* pan/bi: Interpret register allocation resultsAlyssa Rosenzweig2020-03-122-0/+96
| | | | | | | | | | | | Once LCRA has run, we have a map from IR indices to byte offsets into the register file, so we need to "install" these results, rewriting the IR to use native registers and fixing up writemasks/swizzles to substitute vectorization for adjacent registers (for LCRA, we're modeling in terms of real vectors). Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Add register allocatorAlyssa Rosenzweig2020-03-124-1/+116
| | | | | | | | | | We model the machine as vector (with restrictions) to natively handle mixed types and I/O and other goodies. We use LCRA for the heavylifting. This commit adds only the modeling to feed into LCRA and spit LCRA solutions back; next commit will integrate it with the IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Fix missing src_typesAlyssa Rosenzweig2020-03-121-0/+7
| | | | | | | | We want types to be consistent throughout the IR so we don't have to make exceptions to parse things out. These cases just got missed. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Fix vector handling of readmasksAlyssa Rosenzweig2020-03-123-10/+46
| | | | | | | | | | | | The issue was messing with liveness analysis... with Midgard we look at the writemask to decide how the instruction behaves. Here, since our ALU is scalar (except for subdivision which doesn't have proper writemasks anyway) we just look at the component count directly -- either 4 for vector instructions (essentially - for smaller loads we can replicate manually without much burden), or 1 for scalar. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Minor fixes in iteration macrosAlyssa Rosenzweig2020-03-121-9/+9
| | | | | | | Found during RA bringup. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/midgard: Remove incorrect comment in RAAlyssa Rosenzweig2020-03-121-7/+0
| | | | | | | | Ironically, this comment was mistakenly added by the commit that fixed the purported issue in the comment (1bce7fdecd86 - found by `git blame`) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* panfrost: Move lcra to panfrost/utilAlyssa Rosenzweig2020-03-127-4/+3
| | | | | | | We'll want to use it for the Bifrost RA as well. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* glsl/list: use uintptr_t for exec_node_data()'s subtractionRhys Perry2020-03-121-1/+1
| | | | | | | | | | This fixes UBSan warnings when foreach_list_typed_safe() passes NULL: pointer index expression with base 0x000000000000 overflowed to 0xffffffffffffffa8 Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4157> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4157>
* aco: fix uninitialized data error in waitcnt passRhys Perry2020-03-121-1/+1
| | | | | | | | | | Shouldn't create any incorrect waitcnts but may create suboptimial waitcnts in rare cases. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4133> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4133>
* ac/llvm: add missing optimization barrier for 64-bit readlanesSamuel Pitoiset2020-03-121-27/+40
| | | | | | | | | | Otherwise, LLVM optimizes it but it's actually incorrect. Fixes: 0f45d4dc2b1 ("ac: add ac_build_readlane without optimization barrier") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3585> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3585>
* iris: toggle on PIPE_CAP_MIXED_COLOR_DEPTH_BITSTapani Pälli2020-03-121-0/+1
| | | | | | | | | | | This enables additional EGL configs where we have depth/stencil buffer with different number of bits per pixel than color buffer has. This enables some Android games to work that require such config. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127>
* turnip: Add tu6_control struct.Hyunjun Ko2020-03-122-10/+31
| | | | | | | | | | Follow the way that freedreno is doing so that we could see the whole layout of the scratch buffer. Signed-off-by: Hyunjun Ko <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 08:08:04 +0000