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* amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htileMarek Olšák2020-05-077-26/+28
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmaskMarek Olšák2020-05-076-32/+28
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* amd: remove duplicated definitions from amdgpu_drm.hMarek Olšák2020-05-074-19/+0
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* amd: update amdgpu_drm.hMarek Olšák2020-05-071-1/+14
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* llvmpipe: make sample position a global array.Dave Airlie2020-05-073-11/+12
| | | | | | | | | | | | | I messed this up and LLVM asserts on it. Use the gallivm struct wrappers to make it clearer. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2913 Reviewed-by: Erik Faye-Lund <[email protected]> Tested-by: Erik Faye-Lund <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4933>
* nir/algebraic: Optimize some bfe patternsIan Romanick2020-05-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Use -x instead of 32-x in shift counts. Tiger Lake total instructions in shared programs: 17597691 -> 17597405 (<.01%) instructions in affected programs: 224557 -> 224271 (-0.13%) helped: 74 HURT: 17 helped stats (abs) min: 1 max: 71 x̄: 14.36 x̃: 7 helped stats (rel) min: 0.08% max: 1.80% x̄: 0.50% x̃: 0.37% HURT stats (abs) min: 1 max: 141 x̄: 45.71 x̃: 40 HURT stats (rel) min: 0.03% max: 3.55% x̄: 1.20% x̃: 1.14% 95% mean confidence interval for instructions value: -10.53 4.24 95% mean confidence interval for instructions %-change: -0.38% 0.01% Inconclusive result (value mean confidence interval includes 0). total cycles in shared programs: 333595656 -> 333180770 (-0.12%) cycles in affected programs: 70056467 -> 69641581 (-0.59%) helped: 91 HURT: 4 helped stats (abs) min: 1 max: 25174 x̄: 4571.40 x̃: 400 helped stats (rel) min: <.01% max: 2.23% x̄: 0.40% x̃: 0.21% HURT stats (abs) min: 1 max: 370 x̄: 277.75 x̃: 370 HURT stats (rel) min: 0.01% max: 0.04% x̄: 0.04% x̃: 0.04% 95% mean confidence interval for cycles value: -5981.55 -2752.89 95% mean confidence interval for cycles %-change: -0.48% -0.29% Cycles are helped. Ice Lake, Skylake, Broadwell, and Haswell had similar results. (Ice Lake shown) total instructions in shared programs: 16117204 -> 16116723 (<.01%) instructions in affected programs: 207109 -> 206628 (-0.23%) helped: 100 HURT: 0 helped stats (abs) min: 1 max: 9 x̄: 4.81 x̃: 7 helped stats (rel) min: 0.10% max: 1.58% x̄: 0.23% x̃: 0.20% 95% mean confidence interval for instructions value: -5.51 -4.11 95% mean confidence interval for instructions %-change: -0.27% -0.19% Instructions are helped. total cycles in shared programs: 330487341 -> 330082421 (-0.12%) cycles in affected programs: 68037050 -> 67632130 (-0.60%) helped: 89 HURT: 7 helped stats (abs) min: 2 max: 24610 x̄: 4567.07 x̃: 400 helped stats (rel) min: <.01% max: 1.52% x̄: 0.39% x̃: 0.22% HURT stats (abs) min: 1 max: 370 x̄: 221.29 x̃: 170 HURT stats (rel) min: 0.01% max: 1.66% x̄: 0.58% x̃: 0.04% 95% mean confidence interval for cycles value: -5780.79 -2655.05 95% mean confidence interval for cycles %-change: -0.42% -0.22% Cycles are helped. Ivy Bridge total instructions in shared programs: 11873641 -> 11873137 (<.01%) instructions in affected programs: 147464 -> 146960 (-0.34%) helped: 54 HURT: 0 helped stats (abs) min: 9 max: 10 x̄: 9.33 x̃: 9 helped stats (rel) min: 0.29% max: 0.41% x̄: 0.34% x̃: 0.34% 95% mean confidence interval for instructions value: -9.46 -9.20 95% mean confidence interval for instructions %-change: -0.35% -0.33% Instructions are helped. total cycles in shared programs: 175769085 -> 175549519 (-0.12%) cycles in affected programs: 60770592 -> 60551026 (-0.36%) helped: 54 HURT: 0 helped stats (abs) min: 252 max: 13434 x̄: 4066.04 x̃: 1290 helped stats (rel) min: 0.02% max: 0.74% x̄: 0.34% x̃: 0.26% 95% mean confidence interval for cycles value: -5323.59 -2808.48 95% mean confidence interval for cycles %-change: -0.41% -0.27% Cycles are helped. No changes on any earlier Intel platforms. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
* nir/algebraic: Split ibfe and ubfe with two constant sourcesIan Romanick2020-05-073-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I also tried splitting ubfe instructions with one or zero constants, and zero shaders in shader-db were affected. The "lost" shader is a compute shader that was promoted from SIMD8 to SIMD16, so is also counted as the gained shader. v2: Further restrict bfe splitting. bfe with multiple constants is better on at least some Radeon GPUs. Use -x instead of 32-x in shift counts. v3: Fix the outer shift count for ibfe lowering. Add c=0 optimizations to prevent bad lowering. Both suggested by Rhys. Add shift by -32 optimizations. Tiger Lake total instructions in shared programs: 17608764 -> 17596316 (-0.07%) instructions in affected programs: 303765 -> 291317 (-4.10%) helped: 113 HURT: 46 helped stats (abs) min: 1 max: 458 x̄: 120.67 x̃: 21 helped stats (rel) min: 0.09% max: 11.23% x̄: 3.47% x̃: 1.39% HURT stats (abs) min: 1 max: 201 x̄: 25.83 x̃: 6 HURT stats (rel) min: 0.23% max: 5.18% x̄: 1.53% x̃: 1.11% 95% mean confidence interval for instructions value: -101.13 -55.45 95% mean confidence interval for instructions %-change: -2.61% -1.44% Instructions are helped. total cycles in shared programs: 338390770 -> 333530868 (-1.44%) cycles in affected programs: 79438330 -> 74578428 (-6.12%) helped: 112 HURT: 64 helped stats (abs) min: 2 max: 268955 x̄: 44261.93 x̃: 1452 helped stats (rel) min: <.01% max: 29.51% x̄: 4.72% x̃: 2.23% HURT stats (abs) min: 2 max: 17618 x̄: 1522.41 x̃: 84 HURT stats (rel) min: <.01% max: 7.34% x̄: 1.35% x̃: 0.34% 95% mean confidence interval for cycles value: -37232.47 -17993.69 95% mean confidence interval for cycles %-change: -3.37% -1.65% Cycles are helped. total spills in shared programs: 8944 -> 8138 (-9.01%) spills in affected programs: 3240 -> 2434 (-24.88%) helped: 67 HURT: 0 total fills in shared programs: 9373 -> 7842 (-16.33%) fills in affected programs: 4736 -> 3205 (-32.33%) helped: 67 HURT: 0 LOST: 1 GAINED: 2 Ice Lake and Skylake had similar results. (Ice Lake shown) total instructions in shared programs: 16123288 -> 16116876 (-0.04%) instructions in affected programs: 241155 -> 234743 (-2.66%) helped: 126 HURT: 2 helped stats (abs) min: 1 max: 209 x̄: 50.90 x̃: 7 helped stats (rel) min: 0.07% max: 5.94% x̄: 1.76% x̃: 0.65% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.05% max: 0.24% x̄: 0.15% x̃: 0.15% 95% mean confidence interval for instructions value: -61.29 -38.89 95% mean confidence interval for instructions %-change: -2.05% -1.42% Instructions are helped. total cycles in shared programs: 335419163 -> 330438819 (-1.48%) cycles in affected programs: 77515502 -> 72535158 (-6.42%) helped: 139 HURT: 37 helped stats (abs) min: 2 max: 269140 x̄: 36374.19 x̃: 597 helped stats (rel) min: <.01% max: 28.60% x̄: 3.67% x̃: 1.31% HURT stats (abs) min: 4 max: 17618 x̄: 2045.08 x̃: 174 HURT stats (rel) min: 0.02% max: 8.32% x̄: 2.61% x̃: 0.62% 95% mean confidence interval for cycles value: -37799.30 -18795.51 95% mean confidence interval for cycles %-change: -3.13% -1.57% Cycles are helped. total spills in shared programs: 8065 -> 7306 (-9.41%) spills in affected programs: 3153 -> 2394 (-24.07%) helped: 67 HURT: 0 total fills in shared programs: 8710 -> 7412 (-14.90%) fills in affected programs: 4466 -> 3168 (-29.06%) helped: 67 HURT: 0 LOST: 1 GAINED: 1 Broadwell total instructions in shared programs: 14970538 -> 14965967 (-0.03%) instructions in affected programs: 227040 -> 222469 (-2.01%) helped: 126 HURT: 2 helped stats (abs) min: 1 max: 136 x̄: 36.29 x̃: 8 helped stats (rel) min: 0.07% max: 6.02% x̄: 1.47% x̃: 0.89% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.05% max: 0.24% x̄: 0.14% x̃: 0.14% 95% mean confidence interval for instructions value: -43.05 -28.37 95% mean confidence interval for instructions %-change: -1.69% -1.19% Instructions are helped. total cycles in shared programs: 336237662 -> 333035960 (-0.95%) cycles in affected programs: 72066394 -> 68864692 (-4.44%) helped: 134 HURT: 42 helped stats (abs) min: 4 max: 122640 x̄: 24344.54 x̃: 1833 helped stats (rel) min: <.01% max: 26.93% x̄: 4.02% x̃: 2.38% HURT stats (abs) min: 1 max: 17205 x̄: 1439.69 x̃: 92 HURT stats (rel) min: <.01% max: 7.12% x̄: 1.34% x̃: 0.62% 95% mean confidence interval for cycles value: -23753.58 -12629.40 95% mean confidence interval for cycles %-change: -3.50% -1.98% Cycles are helped. total spills in shared programs: 21122 -> 20204 (-4.35%) spills in affected programs: 3644 -> 2726 (-25.19%) helped: 67 HURT: 0 total fills in shared programs: 24879 -> 23460 (-5.70%) fills in affected programs: 4883 -> 3464 (-29.06%) helped: 67 HURT: 0 Haswell total instructions in shared programs: 13148269 -> 13145444 (-0.02%) instructions in affected programs: 137046 -> 134221 (-2.06%) helped: 97 HURT: 3 helped stats (abs) min: 1 max: 137 x̄: 30.58 x̃: 3 helped stats (rel) min: 0.14% max: 4.38% x̄: 1.38% x̃: 0.44% HURT stats (abs) min: 1 max: 70 x̄: 47.00 x̃: 70 HURT stats (rel) min: 0.05% max: 5.82% x̄: 3.90% x̃: 5.82% 95% mean confidence interval for instructions value: -37.15 -19.35 95% mean confidence interval for instructions %-change: -1.56% -0.89% Instructions are helped. total cycles in shared programs: 321221834 -> 318333159 (-0.90%) cycles in affected programs: 54932349 -> 52043674 (-5.26%) helped: 95 HURT: 53 helped stats (abs) min: 4 max: 123390 x̄: 30648.39 x̃: 702 helped stats (rel) min: <.01% max: 28.87% x̄: 4.27% x̃: 2.87% HURT stats (abs) min: 4 max: 2357 x̄: 432.49 x̃: 113 HURT stats (rel) min: <.01% max: 3.44% x̄: 1.03% x̃: 0.54% 95% mean confidence interval for cycles value: -26154.16 -12881.99 95% mean confidence interval for cycles %-change: -3.20% -1.55% Cycles are helped. total spills in shared programs: 19878 -> 19293 (-2.94%) spills in affected programs: 3020 -> 2435 (-19.37%) helped: 41 HURT: 2 total fills in shared programs: 20918 -> 19875 (-4.99%) fills in affected programs: 3968 -> 2925 (-26.29%) helped: 41 HURT: 2 LOST: 0 GAINED: 1 Ivy Bridge total instructions in shared programs: 11875585 -> 11873641 (-0.02%) instructions in affected programs: 78065 -> 76121 (-2.49%) helped: 27 HURT: 0 helped stats (abs) min: 8 max: 134 x̄: 72.00 x̃: 72 helped stats (rel) min: 0.36% max: 4.23% x̄: 2.42% x̃: 2.42% 95% mean confidence interval for instructions value: -83.68 -60.32 95% mean confidence interval for instructions %-change: -2.78% -2.07% Instructions are helped. total cycles in shared programs: 178232734 -> 175769085 (-1.38%) cycles in affected programs: 50018707 -> 47555058 (-4.93%) helped: 27 HURT: 0 helped stats (abs) min: 82035 max: 99953 x̄: 91246.26 x̃: 92278 helped stats (rel) min: 4.40% max: 5.69% x̄: 4.93% x̃: 4.95% 95% mean confidence interval for cycles value: -93674.20 -88818.32 95% mean confidence interval for cycles %-change: -5.09% -4.78% Cycles are helped. total spills in shared programs: 4182 -> 3739 (-10.59%) spills in affected programs: 1089 -> 646 (-40.68%) helped: 27 HURT: 0 total fills in shared programs: 5216 -> 4345 (-16.70%) fills in affected programs: 1874 -> 1003 (-46.48%) helped: 27 HURT: 0 No changes on any earlier Intel platforms. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
* nir/algebraic: Recognize open-coded byte or word extract from bfeIan Romanick2020-05-071-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Move word-extract patterns up near the byte-extract patterns. Suggested by Rhys. Tiger Lake total instructions in shared programs: 21369236 -> 21368712 (<.01%) instructions in affected programs: 913104 -> 912580 (-0.06%) helped: 209 HURT: 165 helped stats (abs) min: 1 max: 30 x̄: 5.35 x̃: 3 helped stats (rel) min: 0.03% max: 6.92% x̄: 0.28% x̃: 0.12% HURT stats (abs) min: 1 max: 18 x̄: 3.61 x̃: 3 HURT stats (rel) min: 0.04% max: 0.87% x̄: 0.16% x̃: 0.12% 95% mean confidence interval for instructions value: -2.04 -0.76 95% mean confidence interval for instructions %-change: -0.14% -0.04% Instructions are helped. total cycles in shared programs: 490161481 -> 490175959 (<.01%) cycles in affected programs: 72557244 -> 72571722 (0.02%) helped: 193 HURT: 189 helped stats (abs) min: 1 max: 14240 x̄: 509.16 x̃: 71 helped stats (rel) min: <.01% max: 13.71% x̄: 0.44% x̃: 0.05% HURT stats (abs) min: 2 max: 4210 x̄: 596.53 x̃: 173 HURT stats (rel) min: <.01% max: 5.59% x̄: 0.54% x̃: 0.14% 95% mean confidence interval for cycles value: -96.33 172.13 95% mean confidence interval for cycles %-change: -0.07% 0.16% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 10780 -> 10782 (0.02%) spills in affected programs: 18 -> 20 (11.11%) helped: 0 HURT: 1 total fills in shared programs: 10396 -> 10370 (-0.25%) fills in affected programs: 2292 -> 2266 (-1.13%) helped: 27 HURT: 1 Ice Lake total instructions in shared programs: 19556356 -> 19555446 (<.01%) instructions in affected programs: 833336 -> 832426 (-0.11%) helped: 400 HURT: 0 helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2 helped stats (rel) min: 0.07% max: 4.42% x̄: 0.14% x̃: 0.10% 95% mean confidence interval for instructions value: -2.42 -2.13 95% mean confidence interval for instructions %-change: -0.18% -0.11% Instructions are helped. total cycles in shared programs: 488026481 -> 488008714 (<.01%) cycles in affected programs: 81581708 -> 81563941 (-0.02%) helped: 193 HURT: 206 helped stats (abs) min: 1 max: 3615 x̄: 576.35 x̃: 131 helped stats (rel) min: <.01% max: 4.50% x̄: 0.49% x̃: 0.22% HURT stats (abs) min: 1 max: 2244 x̄: 453.73 x̃: 170 HURT stats (rel) min: <.01% max: 5.71% x̄: 0.36% x̃: 0.14% 95% mean confidence interval for cycles value: -127.23 38.17 95% mean confidence interval for cycles %-change: -0.12% 0.03% Inconclusive result (value mean confidence interval includes 0). total fills in shared programs: 9935 -> 9908 (-0.27%) fills in affected programs: 2208 -> 2181 (-1.22%) helped: 27 HURT: 0 Skylake total instructions in shared programs: 17766078 -> 17765186 (<.01%) instructions in affected programs: 822017 -> 821125 (-0.11%) helped: 399 HURT: 1 helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2 helped stats (rel) min: 0.07% max: 4.46% x̄: 0.15% x̃: 0.10% HURT stats (abs) min: 12 max: 12 x̄: 12.00 x̃: 12 HURT stats (rel) min: 0.50% max: 0.50% x̄: 0.50% x̃: 0.50% 95% mean confidence interval for instructions value: -2.39 -2.07 95% mean confidence interval for instructions %-change: -0.18% -0.11% Instructions are helped. total cycles in shared programs: 470905548 -> 470907497 (<.01%) cycles in affected programs: 78598491 -> 78600440 (<.01%) helped: 202 HURT: 192 helped stats (abs) min: 1 max: 3690 x̄: 228.98 x̃: 60 helped stats (rel) min: <.01% max: 4.51% x̄: 0.24% x̃: 0.03% HURT stats (abs) min: 1 max: 2260 x̄: 251.05 x̃: 77 HURT stats (rel) min: <.01% max: 5.31% x̄: 0.24% x̃: 0.06% 95% mean confidence interval for cycles value: -45.01 54.90 95% mean confidence interval for cycles %-change: -0.07% 0.05% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 9941 -> 9943 (0.02%) spills in affected programs: 26 -> 28 (7.69%) helped: 0 HURT: 1 total fills in shared programs: 10293 -> 10268 (-0.24%) fills in affected programs: 2391 -> 2366 (-1.05%) helped: 27 HURT: 1 Broadwell total instructions in shared programs: 17463211 -> 17462366 (<.01%) instructions in affected programs: 861444 -> 860599 (-0.10%) helped: 399 HURT: 1 helped stats (abs) min: 1 max: 20 x̄: 2.14 x̃: 2 helped stats (rel) min: 0.03% max: 4.46% x̄: 0.14% x̃: 0.09% HURT stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7 HURT stats (rel) min: 0.33% max: 0.33% x̄: 0.33% x̃: 0.33% 95% mean confidence interval for instructions value: -2.26 -1.97 95% mean confidence interval for instructions %-change: -0.17% -0.10% Instructions are helped. total cycles in shared programs: 507048912 -> 506898243 (-0.03%) cycles in affected programs: 79806433 -> 79655764 (-0.19%) helped: 248 HURT: 136 helped stats (abs) min: 1 max: 8450 x̄: 1124.18 x̃: 64 helped stats (rel) min: <.01% max: 5.91% x̄: 0.83% x̃: 0.05% HURT stats (abs) min: 2 max: 7632 x̄: 942.12 x̃: 103 HURT stats (rel) min: <.01% max: 5.62% x̄: 0.71% x̃: 0.08% 95% mean confidence interval for cycles value: -647.01 -137.73 95% mean confidence interval for cycles %-change: -0.47% -0.10% Cycles are helped. total spills in shared programs: 22996 -> 22998 (<.01%) spills in affected programs: 31 -> 33 (6.45%) helped: 0 HURT: 1 total fills in shared programs: 25951 -> 25923 (-0.11%) fills in affected programs: 2444 -> 2416 (-1.15%) helped: 29 HURT: 1 Haswell total instructions in shared programs: 15841325 -> 15840554 (<.01%) instructions in affected programs: 869679 -> 868908 (-0.09%) helped: 394 HURT: 6 helped stats (abs) min: 1 max: 20 x̄: 2.15 x̃: 2 helped stats (rel) min: 0.06% max: 4.46% x̄: 0.14% x̃: 0.09% HURT stats (abs) min: 7 max: 18 x̄: 12.83 x̃: 13 HURT stats (rel) min: 0.32% max: 0.82% x̄: 0.59% x̃: 0.61% 95% mean confidence interval for instructions value: -2.16 -1.69 95% mean confidence interval for instructions %-change: -0.16% -0.09% Instructions are helped. total cycles in shared programs: 520417167 -> 520279766 (-0.03%) cycles in affected programs: 80949963 -> 80812562 (-0.17%) helped: 246 HURT: 139 helped stats (abs) min: 1 max: 8152 x̄: 790.08 x̃: 129 helped stats (rel) min: <.01% max: 11.46% x̄: 0.70% x̃: 0.09% HURT stats (abs) min: 1 max: 7085 x̄: 409.78 x̃: 80 HURT stats (rel) min: <.01% max: 5.25% x̄: 0.31% x̃: 0.06% 95% mean confidence interval for cycles value: -526.34 -187.43 95% mean confidence interval for cycles %-change: -0.49% -0.18% Cycles are helped. total spills in shared programs: 21714 -> 21729 (0.07%) spills in affected programs: 174 -> 189 (8.62%) helped: 0 HURT: 6 total fills in shared programs: 22136 -> 22132 (-0.02%) fills in affected programs: 2848 -> 2844 (-0.14%) helped: 31 HURT: 6 Ivy Bridge total instructions in shared programs: 15177059 -> 15177003 (<.01%) instructions in affected programs: 79370 -> 79314 (-0.07%) helped: 29 HURT: 0 helped stats (abs) min: 1 max: 2 x̄: 1.93 x̃: 2 helped stats (rel) min: 0.06% max: 0.16% x̄: 0.08% x̃: 0.07% 95% mean confidence interval for instructions value: -2.03 -1.83 95% mean confidence interval for instructions %-change: -0.09% -0.07% Instructions are helped. total cycles in shared programs: 420424359 -> 420417254 (<.01%) cycles in affected programs: 29562648 -> 29555543 (-0.02%) helped: 23 HURT: 6 helped stats (abs) min: 2 max: 2741 x̄: 432.57 x̃: 142 helped stats (rel) min: <.01% max: 0.26% x̄: 0.04% x̃: 0.02% HURT stats (abs) min: 4 max: 1184 x̄: 474.00 x̃: 226 HURT stats (rel) min: <.01% max: 0.11% x̄: 0.05% x̃: 0.05% 95% mean confidence interval for cycles value: -553.48 63.48 95% mean confidence interval for cycles %-change: -0.05% <.01% Inconclusive result (value mean confidence interval includes 0). total fills in shared programs: 6420 -> 6393 (-0.42%) fills in affected programs: 1901 -> 1874 (-1.42%) helped: 27 HURT: 0 No changes on any earlier Intel platforms. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
* gallium/swr: Fix crashes in sampling codeJan Zielinski2020-05-073-0/+8
| | | | | | | | | Add missing functions used by the new sampling code in llvmpipe (num_samples and sample_stride) Reviewed-by: Krzysztof Raszkowski <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4947>
* panfrost: Handle MALI_RGB8_UNORM in panfrost_format_to_bifrost_blendTomeu Vizoso2020-05-071-0/+1
| | | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
* panfrost: Don't trample on top of Bifrost-specific unionsTomeu Vizoso2020-05-071-20/+26
| | | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
* pan/decode: Fix flags_hi printingAlyssa Rosenzweig2020-05-071-1/+1
| | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
* panfrost: Add checksum BOs to batchTomeu Vizoso2020-05-071-2/+14
| | | | | | | | So they don't get released before the last frame finishes rendering. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
* anv: don't expose VK_INTEL_performance_query without kernel supportLionel Landwerlin2020-05-072-1/+3
| | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 2b5f30b1d91b ("anv: implement VK_INTEL_performance_query") Acked-by: Timothy Strelchun <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4937>
* tu: Support pipelines without a fragment shaderConnor Abbott2020-05-072-8/+20
| | | | | | | | Apparently this is allowed, and the CTS started doing this more often recently which resulted in frequent hangs running the entire CTS. I copied the code to create an empty FS from radv. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4928>
* util/os_memory: never use os_memory_debug.hErik Faye-Lund2020-05-072-14/+0
| | | | | | | | | | | | | | | | This is currently broken hard, because this code is being used in more places that it used to be, and fixing that is prohibitively hard right now. This is far from ideal, as it leaves the same inconsistency in the EMBEDDED_DEVICE code-path. But that only used by VMWare, so it's probably better if they fix it, as they know their requirements better than we do. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2911 Fixes: 76f79db3f5d ("util: stop including files from mesa/main") Acked-by: Jose Fonseca <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4919>
* v3d: Include supported DXT formats to enable s3tc/dxt extensionsJose Maria Casanova Crespo2020-05-071-0/+5
| | | | | | | | | | | | | | | | | | | | | DXT1_RGBA and sRGB variants of DXT[135] formats are enabled as valid format on V3D. Once all S3TC formats supported by V3C are enabled the following extensions become exposed by gallium. * GL_ANGLE_texture_compression_dxt3 * GL_ANGLE_texture_compression_dxt5, * GL_EXT_texture_compression_dxt1 * GL_EXT_texture_compression_s3tc * GL_S3_s3tc * GL_EXT_texture_compression_s3tc_srgb This enables 206 passing piglit test related to gl_compressed.*s3tc_dxt Cc: 20.0 20.1 <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
* v3d: Fix swizzle in DXT3 and DXT5 formatsJose Maria Casanova Crespo2020-05-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Swizzles were ignoring the W component of the format DXT3_RGBA and DXT5_RGBA. This fixes 15 piglit tests: spec/!opengl 1.1/copyteximage 2d spec/!opengl 1.2/copyteximage 3d spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba npot spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgba, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgba, border color only spec/arb_texture_cube_map/copyteximage cube spec/arb_texture_cube_map/copyteximage cube samples=2 spec/arb_texture_cube_map/copyteximage cube samples=4 spec/arb_texture_rectangle/copyteximage rect spec/arb_texture_rectangle/copyteximage rect samples=2 spec/arb_texture_rectangle/copyteximage rect samples=4 spec/ext_texture_array/copyteximage 2d_array spec/ext_texture_array/copyteximage 2d_array samples=2 spec/ext_texture_array/copyteximage 2d_array samples=4 Fixes: 469bbd8387d1 "broadcom/vc5: Move the formats table to per-V3D-version compile." Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
* docs/envvars: update RADV_FORCE_FAMILYRhys Perry2020-05-071-1/+1
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
* docs/envvars: document ACO_DEBUGRhys Perry2020-05-071-0/+11
| | | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
* docs: add src/amd/ to sourcetree.htmlRhys Perry2020-05-071-0/+9
| | | | | | | | | | This file doesn't seem to have been updated in years but this was pretty easy to do. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
* clover/nir: Check the result of spirv_to_nirPierre Moreau2020-05-071-0/+5
| | | | | | | Fixes: deb04adf2ae ("clover: add support for passing kernels as nir to the driver") Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4901>
* nir: make fsat return 0.0 with NaN instead of passing it throughRhys Perry2020-05-072-5/+14
| | | | | | | | | This is how lower_fsat and ACO implements fsat and is a more useful definition since it can be exactly created from fmin(fmax(a, 0.0), 1.0). Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3716>
* compiler/spirv: flag nclamp/nmin/nmax as exactRhys Perry2020-05-071-7/+14
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3716>
* docs/features: Add ARB_clear_texture to virglElie Tournier2020-05-071-1/+1
| | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
* virgl: Enable CAP_CLEAR_TEXTURE if host supports itElie Tournier2020-05-072-1/+3
| | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
* virgl: implement ARB_clear_textureElie Tournier2020-05-074-0/+73
| | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
* r600: Fix warning regarding mixing enums and unsigned in ?: expressionGert Wollny2020-05-071-1/+1
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
* r600: remove some unused variables to silence warningsGert Wollny2020-05-072-4/+0
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
* r600/sb: replace memset by using member initialization/assignmentGert Wollny2020-05-076-10/+45
| | | | | | | | Closes #2860 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
* r600: remove unused static functionsGert Wollny2020-05-071-199/+0
| | | | | | | | Related #2860 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
* r600: Annotate some case fallthroughsGert Wollny2020-05-075-19/+26
| | | | | | | | Also fix indentions where aproprate Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
* ci: run radv-fossils with Pitcairn (GFX6) and Bonaire (GFX7) tooSamuel Pitoiset2020-05-071-3/+11
| | | | | | | | | | This job is really small and it shouldn't hurt to cover two more generations. This will prevent breaking the world on GFX6-GFX7 because we don't regularly test these chips. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
* ci: set ACO_DEBUG=validateir,validatera global for RADV testingSamuel Pitoiset2020-05-071-3/+4
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
* ci: remove unused .test-radv-fossilize ruleSamuel Pitoiset2020-05-071-8/+0
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
* anv: increase minUniformBufferOffsetAlignment to 64Arcady Goldmints-Orlov2020-05-061-2/+4
| | | | | | Acked-by: Jason Ekstrand <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4904>
* freedreno/a6xx: enable tiled compressed texturesRob Clark2020-05-061-0/+3
| | | | | | | | I wasn't expecting this to be too useful, since compressed textures are already block based.. but gfxbench gl_fill says otherwise. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
* freedreno/a6xx: compressed blit fixesRob Clark2020-05-061-4/+15
| | | | | | | | width/height are not necessarily aligned to block boundaries, so we need to round up. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
* freedreno/a6xx: Set tfetch correctly for compressed formatsKristian H. Kristensen2020-05-061-4/+1
| | | | | | | The fetchsize is just the blocksize for compressed formats, which gets rid of the ASTC special cases add handles ETC1/2 as well. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
* freedreno/fdl: Align after dividing by block sizeKristian H. Kristensen2020-05-061-13/+9
| | | | | | | | | For compressed formats, we need to align the number of blocks, not the logical number of pixels in the texture. Only compressed formats have block width/height > 1, so we can just unconditionally multiply the alignment by the block width/height. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
* docs: update calendar for 20.1.0-rc2Eric Engestrom2020-05-061-7/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4927>
* ci: Fix the nick used in IRC reporting.Eric Anholt2020-05-062-1/+11
| | | | | | | | | | | | robclark found that we needed unique IDs when multiple runners were trying to report flakes at the same time, but it turns out due to nick limits (16 chars on freenode) we were just getting all the runners appended with "-142" (or whatever the prefix of the pipelines are these days). And, for the new flake reporting from baremetal, all the runners ended up being just "google-freedreno". Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
* ci: Improve the flakes reports on IRC.Eric Anholt2020-05-062-1/+5
| | | | | | | | | We were incorrectly taking the merge-request on non-MR pipelines (the master build after merge) due to a missing '$'. And, for those pipelines, it would be nice to note whether they're for master or a stable branch. Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
* ci: Enable IRC flake reporting on freedreno baremetal boards.Eric Anholt2020-05-064-1/+11
| | | | | | | | | The IRC channel is useful for me to track and ban flaky tests before they irritate people too much. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2654 Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
* ci: Clean up setup of the job-specific env vars in baremetal testing.Eric Anholt2020-05-062-10/+16
| | | | | | | Avoids copy and paste errors when adding more vars. Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
* radeonsi: fix compilation of monolithic PSMarek Olšák2020-05-061-1/+2
| | | | | | | | | | | | | | | This was totally broken. Monolithic PS is only used if FBFETCH or interpolateAtSample are used. When the PS prolog was built, it overwrote ctx->main_fn. Discovered by @eefano. Fixes: 8832a884345686e6a8b2c0c8aa7515ad3f775b9e "radeonsi: move PS LLVM code into si_shader_llvm_ps.c" Closes: #2814 Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4918>
* tgsi_to_nir: translate non-vec4 image stores correctlyMarek Olšák2020-05-061-2/+5
| | | | | | | set the correct number of components for src data and the intrinsic Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4908>
* i965: Fix out-of-bounds access to brw_stage_state::surf_offsetDanylo Piliaiev2020-05-061-23/+29
| | | | | | | | | | | | | | ../src/mesa/drivers/dri/i965/brw_wm_surface_state.c:1378:32: runtime error: index 3503345872 out of bounds for type 'uint32_t [149]' brw_assign_common_binding_table_offsets has the following comment: "Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're unused but also make sure that addition of small offsets to them will trigger some of our asserts that surface indices are < BRW_MAX_SURFACES." Cc: <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4350>
* zink: lower b2b to b2iErik Faye-Lund2020-05-064-1/+67
| | | | | | | | | | | | | | | Zink requires 1-bit booleans, but this requirement was missed before b2b1s started getting automatically inserted. Let's lower these away, to avoid piglit regressions. Fixes the following piglits: - shaders@glsl-vs-if-bool - spec@!opengl 2.0@vertex-program-two-side Fixes: c217ee8d35f ("nir: Insert b2b1s around booleans in nir_lower_to") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2902 Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4903>
* radv/winsys: do not count visible VRAM buffers twice in the budgetSamuel Pitoiset2020-05-062-17/+33
| | | | | | | | | | | | | | | | | The VRAM size returned to apps is computed as follows: vram_size = real_hw_vram_size - visible_vram_size. Visible VRAM buffers should be counted only in the visible VRAM counter and not twice. Buffers with the NO_CPU_ACCESS flag are known to not be mappable, so they are counted in the VRAM counter. Other buffers, with the CPU_ACCESS flag, or without any of both (imported buffers) are counted in the visible VRAM counter because they are mappable. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4834>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 18:53:54 +0000