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* pan/lcra: Allow per-variable bounds to be setAlyssa Rosenzweig2020-05-214-20/+24
| | | | | | | | | | Different variables need to respect different bounds. In general, 16-bytes is okay, but for 4-channel 16-bit vectors, we can't cross 8 byte boundaries (else the swizzles will not be packable after), so we update LCRA to allow this more general form. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/lcra: Remove unused alignment parametersAlyssa Rosenzweig2020-05-214-4/+2
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Ignore dest.type when offseting load swizzleAlyssa Rosenzweig2020-05-211-1/+1
| | | | | | | It's always as-if 32-bit. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Don't generate conversions for fp16 LUTsAlyssa Rosenzweig2020-05-212-6/+21
| | | | | | | | | We can just set the register mode appropriately and then we don't have to care anywhere else, and there's no extra NIR to chew through. Make sure we include sqrt too. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Implement b2f16Alyssa Rosenzweig2020-05-211-8/+17
| | | | | | | ...as iand Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Streamline dest_override handlingAlyssa Rosenzweig2020-05-216-46/+35
| | | | | | | | We can pass it all off to emit time, and let the types in the IR do the heavylifting in the meantime, which is a lot easier to get right. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Remove redundant redundancyAlyssa Rosenzweig2020-05-212-10/+0
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Defer modifier packing until emit timeAlyssa Rosenzweig2020-05-215-216/+171
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Remove promote_float passAlyssa Rosenzweig2020-05-214-86/+0
| | | | | | | Now unused. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Promote imov to fmov on a NIR levelAlyssa Rosenzweig2020-05-211-1/+8
| | | | | | | Avoids dedicated MIR promote_fmov pass which is unnecessary. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Identify scalar integer modsAlyssa Rosenzweig2020-05-213-43/+39
| | | | | | | | Symmetric with vector mods, except for normal which is packed as sign-extend. (flag 2 never seen in the wild) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Use type to determine triviality of a moveAlyssa Rosenzweig2020-05-211-2/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Use src_types to determine size in schedulingAlyssa Rosenzweig2020-05-211-15/+6
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Add abs/neg/shift modifiers to IRAlyssa Rosenzweig2020-05-212-3/+23
| | | | | | | Rather than twiddling them into the ALU packed field. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Explain ld/st sign/zero extensionAlyssa Rosenzweig2020-05-212-4/+6
| | | | | | | Now we know why there are duplicates :-) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Respect !32-bit sizes in RAAlyssa Rosenzweig2020-05-211-4/+8
| | | | | | | So we can take advantage of mediump. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Handle dest up/lower correctly with swizzlesAlyssa Rosenzweig2020-05-211-5/+14
| | | | | | | During emit time. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Include more typesAlyssa Rosenzweig2020-05-214-1/+11
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Remove mir_get_alu_srcAlyssa Rosenzweig2020-05-211-7/+0
| | | | | | | Unused. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Remove mir_*size routinesAlyssa Rosenzweig2020-05-2110-178/+78
| | | | | | | | We'd rather use the actual type information than inferring modes all over the place. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Fix constant combining crashAlyssa Rosenzweig2020-05-211-1/+3
| | | | | | | We need to round up. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* pan/mdg: Handle comparisons in fp16 pathAlyssa Rosenzweig2020-05-211-17/+33
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
* aco: sign-extend the input and identity for 8-bit subgroup operationsSamuel Pitoiset2020-05-211-0/+12
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: use a temporary SGPR for 8-bit/16-bit literal reduction identitiesSamuel Pitoiset2020-05-211-3/+5
| | | | | | | | Otherwise, the compiler overwrites s0 which contains the exec mask. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: implement 8-bit/16-bit nir_intrinsic_quad_*Samuel Pitoiset2020-05-211-0/+16
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: implement 8-bit/16-bit nir_intrinsic_{shuffle,_read_invocation}Samuel Pitoiset2020-05-211-1/+8
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: implement 8-bit/16-bit nir_intrinsic_read_first_invocationSamuel Pitoiset2020-05-211-1/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelaneSamuel Pitoiset2020-05-211-1/+1
| | | | | | | | | | I would expect it to just work as intended and other solutions, like v_and_b32 to make sure the upper bits are 0, might have some overhead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: implement 8-bit/16-bit reductionsSamuel Pitoiset2020-05-214-24/+76
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* aco: declare 8-bit/16-bit reduce operationsSamuel Pitoiset2020-05-212-13/+39
| | | | | | | | The 8-bit float variants are only for consistency but are unused. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
* no_extern_c.h: fix typo in commentEric Engestrom2020-05-211-1/+1
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5145>
* docs: fix broken release-calendarErik Faye-Lund2020-05-211-0/+1
| | | | | | | This also removed the branch-row, which is needed to keep things sane. Fixes: 34718070ef8 ("docs: update calendar for 20.1.0-rc4") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5143>
* aco: fix typo in insert_waitcnt's kill()Rhys Perry2020-05-211-1/+1
| | | | | | | | | No shader-db changes Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3004 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5126>
* aco: don't allow unaligned subdword accesses on GFX6/7Daniel Schürmann2020-05-212-16/+20
| | | | | | | | There are no SDWA instructions which means that only full registers can be accessed. Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
* aco: fix corner case in register allocationDaniel Schürmann2020-05-211-2/+2
| | | | | | | | | We mark dead operands in the register file when searching for a register for a definition. Only do so, if this space has not yet been taken by a different definition. Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
* aco: don't move create_vector subdword operands to unsupported register offsetsDaniel Schürmann2020-05-211-1/+1
| | | | | Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
* aco: restrict copying of create_vector operands to GFX9+Daniel Schürmann2020-05-211-15/+26
| | | | | | | This improves code size for Polaris and earlier due to less register swapping Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
* clover: Address unnecessary copy warningsPierre Moreau2020-05-212-2/+2
| | | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>
* clover/api: Address missing braces for subobj initPierre Moreau2020-05-211-2/+2
| | | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>
* meson: Disable GCC's dead store elimination for memory zeroing custom newDanylo Piliaiev2020-05-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | Some classes use custom new operator which zeroes memory, however gcc does aggressive dead-store elimination which threats all writes to the memory before the constructor as "dead stores". For now we disable this optimization. The new operators in question are declared via: DECLARE_RZALLOC_CXX_OPERATORS DECLARE_LINEAR_ZALLOC_CXX_OPERATORS The issue was found with lto builds, however there is no guarantee that it didn't happen with ordinary ones. CC: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2977 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1358 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5104>
* radv/winsys: remove useless free in radv_amdgpu_create_bo_list()Samuel Pitoiset2020-05-211-3/+1
| | | | | | | | | free(NULL) is fine but let's remove it. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3008 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5131>
* radv: fix duplicated expression in ac_setup_rings()Samuel Pitoiset2020-05-211-1/+1
| | | | | | | | | | Probably a search&replace mistake when that common struct was introduced. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3006 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5130>
* radv: fix missing break in radv_GetPhysicalDeviceFeatures2()Samuel Pitoiset2020-05-211-0/+1
| | | | | | | | | | Wow, missed that one. Fixes: 57e796a12a8 - ("radv: Implement VK_EXT_custom_border_color") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5128>
* aco: fix missing break in label_instruction()Samuel Pitoiset2020-05-211-0/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5129>
* llvmpipe: compute shaders work better with all the threads.Dave Airlie2020-05-211-1/+1
| | | | | | | | | | | I got to benchmarking some vulkan compute benchmark and wondered why my CPUs weren't being saturated, helps if you actually wake up all the threads in the threadpool. Fixes: 1b24e3ba756b (llvmpipe: add compute threadpool + mutex) Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5138>
* dri_util: Update internal_format to GL_RGB8 for MESA_FORMAT_R8G8B8X8_UNORMNataraj Deshpande2020-05-211-1/+1
| | | | | | | | | | | | | | | | The commit helps to resolve GL_INVALID_OPERATION error returned during CTS test when Android format RGBX8888 fallback to RGBA8888 and then set color with glTexSubImage2D(format=GL_RGB). Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests: #SingleLayer_ColorTest_GpuSampledImageCanBeSampled_R8G8B8X8_UNORM Cc: <[email protected]> Fixes: bf576772ab4d ("dri_util: add driImageFormatToSizedInternalGLFormat function") Signed-off-by: Nataraj Deshpande <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5034>
* freedreno/a6xx: Avoid stalling for occlusion queriesKristian H. Kristensen2020-05-214-12/+35
| | | | | | | If we postpone computing the counter delta until after each tile (or sysmem pass), we don't have to stall in the middle of the draw stream. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
* freedreno/a6xx: Emit VFD setup as array writesKristian H. Kristensen2020-05-211-9/+23
| | | | | | | | We can use only one PKT4 for each of VFD_FETCH, VFD_DECODE and VFD_DEST_CNTL and write all the elements if we split the loop into three loops. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
* freedreno/a6xx: Allocate ringbuffer based on VFD countKristian H. Kristensen2020-05-211-7/+7
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
* freedreno/a6xx: Map inputs to VFD entries up frontKristian H. Kristensen2020-05-211-38/+43
| | | | | | | Break this logic out of the loop in preperation for splitting the VFD state emit loop up. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 00:22:03 +0000