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* iris: Build for gen12Jordan Justen2019-08-283-1/+7
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/l3: Don't assert on gen12 (use gen11 config temporarily)Jordan Justen2019-08-281-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* intel/compiler: Disable compaction on gen12 for nowJordan Justen2019-08-281-1/+7
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: build android libmesa_isl for gen12Tapani Pälli2019-08-281-0/+20
| | | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Build gen12 using gen11 code pathsJordan Justen2019-08-284-1/+11
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: generate pack files for gen12 on android buildsTapani Pälli2019-08-281-0/+5
| | | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Build gen12 genxmlJordan Justen2019-08-285-2/+11
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add gen12.xml as a copy of gen11.xmlJordan Justen2019-08-281-0/+7171
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-282-38/+36
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipeJordan Justen2019-08-281-1/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Handle field names with different spacing/hyphenJordan Justen2019-08-281-3/+4
| | | | | | | | | | | | | If a field name differs slightly between two generations then this change will still add the fields into the same group. For example, these will be treated as equal: * "Software Exception" and "Software Exception" * "Per Thread" and "Per-Thread" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* freedreno/a6xx: Fix non-mipmap filtering selection.Eric Anholt2019-08-281-6/+6
| | | | | | | | | | We were clamping the LOD to force non-mipmap filtering, but that means that the HW doesn't get to select between the min and mag filters. Setting MIPFILTER_LINEAR_FAR appears to force non-mipmap filtering. Fixes all failures in dEQP-GLES2.functional.texture.filtering.2d.* Reviewed-by: Rob Clark <[email protected]>
* intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardwareIan Romanick2019-08-281-0/+1
| | | | | | | | | | See the previous commit for the explanation of the Fixes tag. Hurts 21 shaders in shader-db. All of the hurt shaders are in Unreal Engine 4 tech demos. Reviewed-by: Matt Turner <[email protected]> Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
* nir/algrbraic: Don't optimize open-coded bitfield reverse when lowering is ↵Ian Romanick2019-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | enabled This caused a problem on Sandybridge where an open-coded bitfieldReverse() function could be optimized to a nir_op_bitfield_reverse that would generate an unsupported BFREV instruction in the backend. This was encountered in some Unreal4 tech demos in shader-db. The bug was not previously noticed because we don't actually try to run those demos on Sandybridge. The fixes tag is a bit a lie. The actual bug was introduced about 26,000 commits earlier in 371c4b3c48f ("nir: Recognize open-coded bitfield_reverse."). Without the NIR lowering pass, the flag needed to avoid the optimization does not exist. Hopefully nobody will care to fix this on an earlier Mesa release. Reviewed-by: Matt Turner <[email protected]> Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
* gallium: Don't emit identical endian-dependent pack/unpack code.Eric Anholt2019-08-281-5/+11
| | | | | | | | | Reduces the size of the u_format_table.c file by 140k (out of 1.64M) and makes me less confused about endianness in gallium. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Fix big-endian addressing of non-bitmask array formats.Eric Anholt2019-08-282-6/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | The formats affected are: - LA x (16_FLOAT, 32_FLOAT, 32_UINT, 32_SINT) - R8G8B8 x (UNORM, SNORM, SRGB, USCALED, SSCALED, UINT, SINT) - RG/RGB/RGBA x (64_FLOAT, 32_FLOAT, 16_FLOAT, 32_UNORM, 32_SNORM, 32_USCALED, 32_SSCALED, 32_FIXED, 32_UINT, 32_SINT) - RGB/RGBA x (16_UNORM, 16_SNORM, 16_USCALED, 16_SSCALED, 16_UINT, 16_SINT) - RGBx16 x (UNORM, SNORM, FLOAT, UINT, SINT) - RGBx32 x (FLOAT, UINT, SINT) - RA x (16_FLOAT, 32_FLOAT, 32_UINT, 32_SINT) The updated st_formats.c unit test checks that the formats affected by this change are all array formats in the equivalent Mesa format (if any). Mesa's array format definition is clear: the value stored is an array (increasing memory address) of values of the channel's type. It's also the only thing that makes sense for the RGB types, or very large types like RGBA64_FLOAT (A should not move to the low address because the cpu is BE). Acked-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Tested-by: Matt Turner <[email protected]> (unit tests on BE) Reviewed-by: Marek Olšák <[email protected]>
* gallium: Drop a bit of dead code from the pack/unpack python.Eric Anholt2019-08-281-2/+0
| | | | | | | | Nothing used this var. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Drop the useless union wrapper on pack/unpack.Eric Anholt2019-08-281-28/+22
| | | | | | | | | Nothing accessed the .value field, just the .chan. Unwrap all the code from the union, for clarity (and 13k less generated code). Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Skip generating the pack/unpack union if we don't use it.Eric Anholt2019-08-281-1/+1
| | | | | | | | | Shaves 30k off of the 1.6M .c file, and makes for less noise for me trying to understand how gallium formats actually work. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Fix mesa format name in unit test failure path.Eric Anholt2019-08-281-1/+1
| | | | | | | | We clearly wanted the mesa format here. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Adam Jackson <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* panfrost: Reset the damage area on imported resourcesBoris Brezillon2019-08-281-11/+12
| | | | | | | | Reset the damage area in the resource_from_handle() path (as done in panfrost_resource_create()). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use ralloc() to allocate instructions to avoid leaking those objsBoris Brezillon2019-08-288-16/+17
| | | | | | | | | Instructions attached to blocks are never explicitly freed. Let's use ralloc() to attach those objects to the compiler context so that they are automatically freed when the ctx object is freed. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* scons: Make GCC builds stricter.Jose Fonseca2019-08-281-1/+4
| | | | | | | | | | Uses some of the same -Werror options used by Meson, as suggested by Michel Dänzer. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* util: Prevent strcasecmp macro redefinion.Jose Fonseca2019-08-281-0/+3
| | | | | | | | MinGW headers already define it. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* util: Prevent implicit declaration of function getenv.Jose Fonseca2019-08-281-0/+1
| | | | | | | | With MinGW cross compilation. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* glx: Fix incompatible function pointer types.Jose Fonseca2019-08-281-1/+1
| | | | | | | | | | | I don't know how Meson didn't hit this issue, when it too already uses -Werror=incompatible-pointer-types Fixes: 3dd299c3d5b88114894e ("glx: Sync <GL/glxext.h> with Khronos") Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* lima: fix texture descriptor issuesVasily Khoruzhick2019-08-282-17/+13
| | | | | | | | | | | Looks like initial RE was wrong and some fields have different purpose. I.e. there's no "disable_mipmap" field, it's actually part of another field that selects mipmap filtering. Also fix layout position. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Drop swizzling parameter from s8_offset.Kenneth Graunke2019-08-271-19/+3
| | | | This is always false on Gen8+, no need for dead code and parameters.
* mesa: Fix _mesa_float_to_unorm() on 32-bit systems.Kenneth Graunke2019-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CTS test on 32-bit systems: GTF-GL46.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_init It does glGetTexImage of a 16-bit SNORM image, requesting 32-bit UNORM data. In get_tex_rgba_uncompressed, we round trip through float to handle image transfer ops for clamping. _mesa_format_convert does: _mesa_float_to_unorm(0.571428597f, 32) which translated to: _mesa_lroundevenf(0.571428597f * 0xffffffffu) which produced different results on 64-bit and 32-bit systems: 64-bit: result = 0x92492500 32-bit: result = 0x80000000 This is because the size of "long" varies between the two systems, and 0x92492500 is too large to fit in a signed 32-bit integer. To fix this, we switch to the new _mesa_i64roundevenf function which always does the 64-bit operation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104395 Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* util: Add a _mesa_i64roundevenf() helper.Kenneth Graunke2019-08-271-0/+16
| | | | | | | | | This always returns a int64_t, translating to _mesa_lroundevenf on systems where long is 64-bit, and llrintf where "long long" is needed. Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glx: Unset the direct_support bit for GLX_EXT_import_contextAdam Jackson2019-08-271-1/+1
| | | | | | | GLX_EXT_import_context operates only on indirect contexts, a direct context cannot possibly support it. Without this change the extension will appear in the combined GLX extension string even if it is missing from the server string, indicating a lack of required server support.
* util: add auxv based PowerPC AltiVec/VSX detectionDaniel Kolesa2019-08-271-4/+25
| | | | | | | | | | | | At least on Linux, we can use the ELF auxiliary vector to detect the presence of AltiVec, VSX and other CPU features without having to go through handling SIGILL, which has various problems of its own. A similar thing is already being done for ARM to detect NEON. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Daniel Kolesa <[email protected]>
* intel/compiler: Use new Gen11 headerless RT writes for MRT casesKenneth Graunke2019-08-271-2/+13
| | | | | | | | | | | | | | | Gen11 adds support for specifying the render target index and src0 alpha present bits in the extended message descriptor. Previously, we had to use a message header for this, requiring extra instructions to write the fields, and two registers of extra payload. Improves performance on my ICL 8x8 frequency locked to 700Mhz, on iris: GfxBench5 Manhattan 3.0: 2.13635% +/- 0.159859% (n=5) GfxBench5 Aztec Ruins: 1.57173% +/- 0.128749% (n=5) Synmark2 OglDeferred: 2.86914% +/- 0.191211% (n=10) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Use generic SEND for Gen7+ FB writesKenneth Graunke2019-08-272-6/+28
| | | | | | | | This takes care of generate_fb_write/fire_fb_write/brw_fb_WRITE's stuff earlier in the visitor. It will also make it easier to generate SENDSC messages with indirect extended descriptors in a few patches. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Refactor FB write message control setup into a helper.Kenneth Graunke2019-08-273-26/+37
| | | | | | This will be used by visitor code to convert directly to SEND in a bit. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Handle bits 15:12 in brw_send_indirect_split_message()Kenneth Graunke2019-08-271-2/+12
| | | | | | | | | | | | Annoyingly, these bits exist in some extended message descriptors (in particular render target writes), but they don't have any corresponding bits in the ISA encoding. So we can't use an immediate and have to fall back to an indirect extended descriptor. Thanks to Jason Ekstrand for reminding me that you can still set these bits via an indirect descriptor, even if they don't exist in the ISA. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Fix src0/desc setter orderingKenneth Graunke2019-08-271-2/+2
| | | | | | | | | | | | | | src0 vstride and type overlap with bits of the extended descriptor. brw_set_desc() also sets the extended descriptor to 0. So by setting the descriptor, then setting src0, we were accidentally setting a bunch of extended descriptor bits unintentionally. When using this infrastructure for framebuffer writes (in a future patch), this ended up setting the extended descriptor bit 20, which is "Null Render Target" on Icelake, causing nothing to be written to the framebuffer. Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: fix scratch buffer WAVESIZE setting leading to corruptionMarek Olšák2019-08-273-31/+39
| | | | | Cc: 19.2 19.1 <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: unbind blend/DSA/rasterizer state correctly in delete functionsMarek Olšák2019-08-271-1/+9
| | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111414 Fixes: b758eed9c37 ("radeonsi: make sure that blend state != NULL and remove all NULL checking") Cc: 19.2 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: align scratch and ring buffer allocations for faster memory accessMarek Olšák2019-08-273-7/+11
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: consolidate determining VGPR_COMP_CNT for API VSMarek Olšák2019-08-271-44/+32
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flagsMarek Olšák2019-08-275-18/+59
| | | | | | | | | | We need two different values of the register, one for NGG and one for legacy, in order to fix edge flags for the legacy pipeline. Passing the ngg flag to emit_clip_regs would be too complicated, so CONTEXT_REG_RMW is used for partial register updates. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variablesMarek Olšák2019-08-274-21/+14
| | | | | | It varies depending on si_shader_key::as_ngg. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add PKT3_CONTEXT_REG_RMWMarek Olšák2019-08-272-0/+31
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* winsys/amdgpu+radeon: process AMD_DEBUG in addition to R600_DEBUGMarek Olšák2019-08-272-4/+8
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: add AMD_DEBUG=nonggMarek Olšák2019-08-272-1/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: finish up Navi14, add PCI IDMarek Olšák2019-08-272-1/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: always use the legacy pipeline for streamoutMarek Olšák2019-08-271-1/+1
| | | | | | The best way to prevent GDS hangs is not to use GDS. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0Marek Olšák2019-08-271-1/+2
| | | | | | Only gfx9 and older use it to get InstanceID in VGPR1. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix InstanceID for legacy VS+GSMarek Olšák2019-08-271-4/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
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