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* anv: add a new execution mode for secondary command buffersLionel Landwerlin2020-05-202-5/+68
* anv: don't reserve a particular register for draw countLionel Landwerlin2020-05-202-40/+46
* intel/mi-builder: add framework for self modifying batchesLionel Landwerlin2020-05-201-0/+69
* intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMMLionel Landwerlin2020-05-201-8/+12
* gitlab: Ask about reproduction rate in the issue templateDenys2020-05-201-1/+1
* nir: Add const to nir_intrinsic_src_componentsJason Ekstrand2020-05-191-1/+1
* pan/mdg: Apply outmodsAlyssa Rosenzweig2020-05-191-0/+39
* pan/mdg: Use helpers for branch/discard inversionAlyssa Rosenzweig2020-05-191-2/+18
* pan/mdg: Remove invert optimizationsAlyssa Rosenzweig2020-05-197-462/+1
* pan/mdg: Treat inot as a modifierAlyssa Rosenzweig2020-05-195-8/+105
* pan/mdg: Apply abs/neg modifiersAlyssa Rosenzweig2020-05-191-0/+9
* pan/mdg: Ingest fsat_signed/fclamp_posAlyssa Rosenzweig2020-05-192-0/+9
* pan/mdg: Prepare for modifier helpersAlyssa Rosenzweig2020-05-192-87/+75
* pan/mdg: Drop nir_lower_to_source_modsAlyssa Rosenzweig2020-05-191-5/+0
* pan/mdg: Remove .pos propagation passAlyssa Rosenzweig2020-05-191-90/+0
* panfrost: Add modifier detection helpersAlyssa Rosenzweig2020-05-194-0/+134
* nir: Add fclamp_pos opcodeAlyssa Rosenzweig2020-05-191-0/+1
* nir: Add fsat_signed opcodeAlyssa Rosenzweig2020-05-191-0/+1
* tu: Support VK_FORMAT_FEATURE_BLIT_SRC_BIT for texture-only formatsConnor Abbott2020-05-191-2/+2
* tu: Fix buffer compressed pitch calculation with unaligned sizesConnor Abbott2020-05-191-13/+18
* tu: Fall back to 3d blit path for BC1_RGB_* formatsConnor Abbott2020-05-191-1/+11
* tu: Always initialize image_view fields for blit sourcesConnor Abbott2020-05-191-26/+28
* nir: Add a store_reg helper and use the builder in phis_to_regsJason Ekstrand2020-05-192-21/+25
* nir: Add a new helper for iterating phi sources leaving a blockJason Ekstrand2020-05-193-15/+30
* nir/clone: Re-use clone_alu for nir_alu_instr_cloneJason Ekstrand2020-05-191-21/+17
* radv/winsys: Finish mapping for sparse residency.Bas Nieuwenhuizen2020-05-191-21/+42
* intel/drm-shim: Return correct values for I915_PARAM_HAS_ALIASING_PPGTTIan Romanick2020-05-191-1/+6
* intel/drm-shim: Add noop ioctl handler for set_tilingIan Romanick2020-05-191-0/+1
* radv: Expose VK_EXT_pipeline_creation_cache_control.Bas Nieuwenhuizen2020-05-193-0/+8
* radv: Support VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT.Bas Nieuwenhuizen2020-05-192-18/+39
* radv: Support VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT.Bas Nieuwenhuizen2020-05-191-0/+12
* radv: Support VK_PIPELINE_COMPILE_REQUIRED_EXT.Bas Nieuwenhuizen2020-05-193-12/+32
* panfrost: Enable AFBC for Z24X8Alyssa Rosenzweig2020-05-191-5/+2
* panfrost: Fix Z24 vs Z32 mixupAlyssa Rosenzweig2020-05-195-13/+6
* panfrost: Switch formats to tableAlyssa Rosenzweig2020-05-197-269/+288
* pan/mfbd: Add format codes for PIPE_FORMAT_B5G5R5A1_UNORMAlyssa Rosenzweig2020-05-191-1/+7
* nir/opt_if: use nir_src_as_bool in opt_peel_loop_initial_if helperRhys Perry2020-05-191-12/+10
* nir/opt_if: run opt_peel_loop_initial_if after all other optimizationsRhys Perry2020-05-197-17/+44
* nir: Add documentation for each jump instruction typeJason Ekstrand2020-05-191-0/+18
* nir: Use a switch statement in nir_handle_add_jumpJason Ekstrand2020-05-191-13/+20
* nir: Validate jump instructions as an instruction typeJason Ekstrand2020-05-191-30/+39
* radv/aco: enable storageInputOutput16 on GFX9+Samuel Pitoiset2020-05-191-2/+2
* aco: fix off-by-one error with 16-bit MTBUF opcodes on GFX10Samuel Pitoiset2020-05-191-1/+1
* aco: implement 16-bit interpSamuel Pitoiset2020-05-191-4/+34
* aco: emit v_interp_*_f16 instructions as VOP3 instead of VINTRPSamuel Pitoiset2020-05-191-14/+42
* aco: validate v_interp_*_f16 as VOP3 instructions instead of VINTRPSamuel Pitoiset2020-05-191-2/+13
* aco: implement 16-bit vertex fetches with tbuffer_load_format_d16_*Samuel Pitoiset2020-05-191-17/+39
* aco: implement 8-bit/16-bit mov's with p_create_vectorSamuel Pitoiset2020-05-191-6/+8
* aco: allow to load/store 16-bit values in VMEM for tess and geomSamuel Pitoiset2020-05-191-3/+3
* aco: convert 16-bit values before exporting MRTsSamuel Pitoiset2020-05-191-2/+39
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