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* radv/gfx10: don't emit PFP packets on ME.Dave Airlie2019-07-081-2/+3
| | | | | | | | | | | This was done for all previous GPUs. This fixes Talos Principle launch hangs. Fixes: 7e43022e8c8 (radv/gfx10: add gfx10_cs_emit_cache_flush) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: select the GFX ring when halting waves with UMR on GFX10Samuel Pitoiset2019-07-084-6/+11
| | | | | | | | GFX10 has two rings, so UMR want to know which one to halt. Select the first one by default. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: Move NGG output handling outside of giant if-statement.Bas Nieuwenhuizen2019-07-081-2/+10
| | | | | | | | | | | | In merged shaders we put a big if around each shader, so both stages can have a different number of threads. However, the NGG output code still needs to run if the first shader is not executed. This can happen when there are more gs threads than vs/es threads, or when there are 0 es/vs threads (why? no clue). Fixes: ee21bd7440c "radv/gfx10: implement NGG support (VS only)" Reviewed-by: Dave Airlie <[email protected]>
* radv: Actually use VK formats for the format table.Bas Nieuwenhuizen2019-07-071-48/+20
| | | | | | | | No ETC2 or ASTC on navi so nothing to add. Fixes: 3dc5ec5d167 "radv/gfx10: generate gfx10_format_table.h" Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* anv: fix VkExternalBufferProperties for host allocationChia-I Wu2019-07-071-0/+10
| | | | | | | | | It was reported as unsupported previously. It should be importable and is compatible with itself. Signed-off-by: Chia-I Wu <[email protected]> Fixes: 69cc6272fbc199 ("anv: Implement VK_EXT_external_memory_host") Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: fix VkExternalBufferProperties for unsupported handlesChia-I Wu2019-07-071-1/+7
| | | | | | | | compatibleHandleTypes must include the queried handle type. Signed-off-by: Chia-I Wu <[email protected]> Cc: <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: Handle cmask being disallowed by addrlib.Bas Nieuwenhuizen2019-07-071-0/+5
| | | | | | | alignment=0 does weird things with align64. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14Samuel Pitoiset2019-07-071-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: Use GS rectlist when needed.Bas Nieuwenhuizen2019-07-071-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: implement NGG support (VS only)Samuel Pitoiset2019-07-076-22/+610
| | | | | | | | | | This needs to be cleaned up a bit, and it probably contains missing stuff and/or bugs. This doesn't fix the "half of the triangles" issue. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Combine vs and tes output keys parts.Bas Nieuwenhuizen2019-07-074-46/+48
| | | | | | That way the same deref is valid for both shader stages. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: Use new uconfig reg index packet for GFX10+.Bas Nieuwenhuizen2019-07-074-6/+18
| | | | | | Otherwise the hardware/firmware seems to not set the registers. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: Set MEM_ORDERED flags on shaders.Bas Nieuwenhuizen2019-07-071-0/+9
| | | | | | Scattered because depending on stage they are at offset 24/25/27/30. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeSamuel Pitoiset2019-07-072-4/+44
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: double the number of tessellation offchip buffers per SESamuel Pitoiset2019-07-071-3/+5
| | | | | | | | Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale the number of offchip buffers accordingly. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: require LLVM 9+Samuel Pitoiset2019-07-071-0/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable geometry and tessellation shadersSamuel Pitoiset2019-07-071-2/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable binningSamuel Pitoiset2019-07-071-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable CLEAR_STATESamuel Pitoiset2019-07-072-5/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable VK_EXT_transform_feedbackSamuel Pitoiset2019-07-071-1/+1
| | | | | | | It requires a bunch of work, so disable for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set user data base registersSamuel Pitoiset2019-07-071-17/+26
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: add gfx10_cs_emit_cache_flushSamuel Pitoiset2019-07-071-1/+174
| | | | | | | | The cache flush logic on GFX10 is quite different and it's implemented with a new function. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set the DCC constant encoding flagSamuel Pitoiset2019-07-071-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: do not declare streamout SGPRSSamuel Pitoiset2019-07-071-0/+3
| | | | | | | Streamout is completely different on GFX10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: do not set stream output shader configSamuel Pitoiset2019-07-071-7/+7
| | | | | | | Transform feedback is really different on GFX10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initializationSamuel Pitoiset2019-07-072-1/+3
| | | | | | | The value doesn't need to be updated for tess. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: update shader-related fields in si_emit_graphics()Samuel Pitoiset2019-07-071-0/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement si_emit_compute()Samuel Pitoiset2019-07-071-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: mask DCC tile swizzle by alignmentSamuel Pitoiset2019-07-071-1/+4
| | | | | | | | | DCC alignment can be less than the alignment of the main surface. In that case, the DCC tile swizzle needs to be masked accordingly. Should have no impact on pre-gfx10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETSamuel Pitoiset2019-07-071-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_flush_vertex_descriptors() changeSamuel Pitoiset2019-07-071-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement fill_geom_tess_rings()Samuel Pitoiset2019-07-071-20/+57
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_CmdBindDescriptorSets()Samuel Pitoiset2019-07-071-3/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement write_buffer_descriptor()Samuel Pitoiset2019-07-071-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: use the correct register for image descriptor dumpingSamuel Pitoiset2019-07-071-2/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_pipeline_generate_hw_hs()Samuel Pitoiset2019-07-071-5/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_fill_shader_variant()Samuel Pitoiset2019-07-071-2/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_pipeline_generate_geometry_shader()Samuel Pitoiset2019-07-071-3/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_init_sampler()Samuel Pitoiset2019-07-071-6/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: fix PS exports for SPI_SHADER_32_ARSamuel Pitoiset2019-07-071-3/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_get_device_name()Samuel Pitoiset2019-07-071-0/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set RADV_FORCE_FAMILYSamuel Pitoiset2019-07-071-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0Samuel Pitoiset2019-07-071-0/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set PA_SC_TILE_STEERING_OVERRIDESamuel Pitoiset2019-07-071-0/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set cache control registersSamuel Pitoiset2019-07-071-0/+21
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set llvm_has_working_vgpr_indexingSamuel Pitoiset2019-07-071-3/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: update DB_DFSM_CONTROL registerSamuel Pitoiset2019-07-071-2/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: update DB_Z_INFO registerSamuel Pitoiset2019-07-071-2/+2
| | | | | | | GFX10 uses the same register as GFX8. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_emit_global_shader_pointers()Samuel Pitoiset2019-07-071-1/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_emit_tess_factor_ring()Samuel Pitoiset2019-07-071-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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