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* egl/android: Align channel masks in HAL_PIXEL_FORMAT tableChad Versace2017-05-311-4/+4
| | | | | | | Improves readability. No change in behavior. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl/drm: remove temporary fd variableEric Engestrom2017-05-311-8/+6
| | | | | | | | | | | | In all codepaths, this var ends up assigned to the struct, except one: a cleanup codepath, where the `close()` was removed, leading to fd leaks. Remove the temp fd and assign to the struct field directly instead. CovID: 1213930 Fixes: 7ec07beedf486d8ab901 ("egl/drm: make use of the dri2_display_destroy() helper") Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* mesa: throw an INVALID_OPERATION error in get_texobj_by_name()Samuel Pitoiset2017-05-311-50/+11
| | | | | | | | Because get_texobj_by_name() can already throw a INVALID_ENUM error, it makes more sense to add a check directly there. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add new 'name' parameter to get_texobj_by_name()Samuel Pitoiset2017-05-311-13/+12
| | | | | | | | To display better function names when INVALID_OPERATION is returned. Requested by Timothy. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: remove unused si_pm4_state::compute_pktSamuel Pitoiset2017-05-312-4/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove chip_class define from si_pm4.hSamuel Pitoiset2017-05-311-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: merge si_pm4_free_state_simple() into si_pm4_free_state()Samuel Pitoiset2017-05-312-8/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/util: fix arithmetic use of 'void *' in u_vector_foreachSamuel Pitoiset2017-05-311-1/+1
| | | | | | | | | | u_vector_foreach is currently only used by the Intel Vulkan driver but when this macro is used in mesa core, GCC reports a compile-time error. Probably because some compiler options are different. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: remove _mesa from static function namesTimothy Arceri2017-05-311-4/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa/st: indentation tidy-upTimothy Arceri2017-05-311-33/+32
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno/a5xx: drop WFIs in emit_marker5()Rob Clark2017-05-301-5/+0
| | | | | | | | | Results in always having at least one WFI between draws, which was slowing stk down by ~5% and ~10% in xonotic. (also drop bogus assert while we're at it.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: timestamp / time-elapsed queriesRob Clark2017-05-302-1/+97
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rename query result structRob Clark2017-05-301-23/+22
| | | | | | Going to want the same thing for timestamp queries. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-05-306-18/+624
| | | | Signed-off-by: Rob Clark <[email protected]>
* i965: Delete dead old-school packing structs.Kenneth Graunke2017-05-301-175/+0
| | | | Trivial.
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-2/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: whitespace changesTim Rowley2017-05-303-8/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-3/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: allow early-z if shader uses depth valueTim Rowley2017-05-301-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: move wireframe/point triangle binning after cullingTim Rowley2017-05-301-80/+76
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: remove unused functionsTim Rowley2017-05-301-28/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-60/+64
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: move binner utility functions to binner.hTim Rowley2017-05-303-193/+225
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix/use SIMD16 calcDeterminantIntVertical()Tim Rowley2017-05-303-43/+65
| | | | | | Stop double pumping the SIMD8 version. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add renderTargetArrayIndex to SWR_PS_CONTEXTTim Rowley2017-05-302-5/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: make simd16 logicops avx512f safeTim Rowley2017-05-301-4/+10
| | | | | | Express the simd16 logicops in terms of avx512f instructions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - add SIMD16 types to jitterTim Rowley2017-05-303-10/+11
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix PA_STATE_OP::Reset()Tim Rowley2017-05-301-0/+3
| | | | | | Fixes instanced GS. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - simplify/refactor StreamOutTim Rowley2017-05-301-42/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix conservative rasterizationTim Rowley2017-05-301-0/+32
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - interleaved simdvertex output in GSTim Rowley2017-05-302-20/+31
| | | | | | Eliminates conversion copies on GS output from simdvertex to simd16vertex. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsicsTim Rowley2017-05-301-4/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - primitive assembly simplificationTim Rowley2017-05-302-50/+32
| | | | | | | | | | | Reduce/simplify vertex storage usage in PA_STATE_OPT, fix PA GetNextVSOutput wrap-around behaviour and eliminate unnecessary SIMDVERTEX copies/storage for tri fan in PA_STATE_OPT Fixes the OpenGL tri fan test failure under SIMD16 - triangle-rasterization-overdraw. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: silence write of cfg graphTim Rowley2017-05-301-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add CreateDirectoryPath to recursively create directoriesTim Rowley2017-05-303-8/+53
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add support for DX1_RGB{_SRGB} formatsTim Rowley2017-05-303-37/+93
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: clean up whitespaceTim Rowley2017-05-301-1/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: adjust BinPostSetupPoints* function signatureTim Rowley2017-05-301-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: remove extra pixel center adjustment in BinPostSetupPointsTim Rowley2017-05-301-5/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* anv: Port over CACHE_MODE_1 optimization fix enables from brw.Kenneth Graunke2017-05-301-0/+13
| | | | | | | | | Ben and I haven't observed these to help anything, but they enable hardware optimizations for particular cases. It's probably best to enable them ahead of time, before we run into such a case. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke2017-05-301-0/+30
| | | | | | | | | These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Set the "Float Blend Optimization Enable" bit on Gen9+.Kenneth Graunke2017-05-302-1/+4
| | | | | | | | | | | | | | | | | This is woefully undocumented. It's some kind of optimization that avoids unnecessary render target reads when blending with a floating point render target, using independent alpha blending modes. The internal documentation indicates that this bit exists on Cherryview as well, but the other driver doesn't appear to set it on that platform. There's also some confusing wording that indicates that it may exist on Broadwell, but the documentation says it's reserved, so who knows. I was not able to find any workload that benefited from setting this bit, but it seems like a good idea to set it nonetheless. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Fix type of brw_context::render_target_format[]Chad Versace2017-05-303-5/+5
| | | | | | | | | It's an array of isl_format, not uint32_t. This patch updates every reference to render_target_format[] git-grep. Trivial cleanup. No change in behavior. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Move func to right comment block in brw_context.hChad Versace2017-05-301-1/+1
| | | | | | | brw_init_surface_formats() is defined in brw_surface_formats.c, not brw_wm_surface_state.c. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Document type of GLuint __DRIimage::formatChad Versace2017-05-301-1/+1
| | | | | | It's either a mesa_format or mesa_array_format. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Add whitespace in intel_update_image_buffers()Chad Versace2017-05-301-0/+1
| | | | | | Improve readability. Add an empty line between two large 'if' blocks. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Move an 'i' declaration into its 'for' loopChad Versace2017-05-301-2/+2
| | | | | | | In intel_update_dri2_buffers(). Trivial cleanup. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Fix type of intel_update_image_buffers::formatChad Versace2017-05-301-1/+1
| | | | | | It's a mesa_format, not an unsigned int. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Rename intel_create_renderbufferChad Versace2017-05-303-8/+9
| | | | | | | The name is misleading because the function is unrelated to GL renderbuffers. Rename it to intel_create_winsys_renderbuffer. Reviewed-by: Tapani Pälli <[email protected]>
* i965/dri: Combine declaration and assignment in intelCreateBufferChad Versace2017-05-301-2/+1
| | | | | | Trivial cleanup. Reviewed-by: Tapani Pälli <[email protected]>
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