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* gallium/screen: Add pipe_screen::resource_get_paramJordan Justen2019-08-132-0/+25
* vc4: clamp gl_PointSize to a minimum of 1.0Iago Toral Quiroga2019-08-131-5/+3
* v3d: clamp gl_PointSize to a minimum of 1.0Iago Toral Quiroga2019-08-131-0/+5
* nir: add a pass to clamp gl_PointSize to a rangeIago Toral Quiroga2019-08-133-0/+127
* v3d: line length style fixesIago Toral Quiroga2019-08-131-26/+33
* v3d: honor the write mask on store operationsIago Toral Quiroga2019-08-131-85/+120
* v3d: refactor ntq_emit_tmu_general() slightlyIago Toral Quiroga2019-08-131-24/+36
* v3d: do not automatically flush current job for SSBOs and shader imagesIago Toral Quiroga2019-08-135-41/+90
* v3d: only process glMemoryBarrier() for SSBOs and imagesIago Toral Quiroga2019-08-131-1/+7
* v3d: fix flushing of SSBOs and shader imagesIago Toral Quiroga2019-08-131-3/+9
* intel/tools: Fix aub_file initialization in intel_dump_gpuCaio Marcelo de Oliveira Filho2019-08-121-0/+6
* i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.Rafael Antognolli2019-08-122-0/+88
* anv/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.Rafael Antognolli2019-08-123-0/+78
* iris/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.Rafael Antognolli2019-08-121-1/+80
* intel: Get information about pixel pipes subslices.Rafael Antognolli2019-08-122-1/+25
* intel/gen_decoder: Decode SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-0/+8
* intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-1/+33
* anv: Implement VK_KHR_pipeline_executable_propertiesJason Ekstrand2019-08-125-4/+295
* anv: Add a ralloc context to anv_pipelineJason Ekstrand2019-08-123-0/+9
* anv: Force a full re-compile when CAPTURE_INTERNAL_REPRESENTATION_TEXT is setJason Ekstrand2019-08-123-57/+75
* anv/pipeline: Split setting up per-stage keys into its own loopJason Ekstrand2019-08-121-3/+8
* anv: Record shader compile stats in the pipeline cacheJason Ekstrand2019-08-124-9/+59
* anv/pipeline: Stash generated code in the pipeline stageJason Ekstrand2019-08-121-42/+47
* intel/fs: Add SLM size to brw_cs_prog_dataJason Ekstrand2019-08-122-0/+2
* intel/compiler: Fill a compiler statistics structJason Ekstrand2019-08-1219-40/+89
* freedreno: disable tiling for cubemapsKhaled Emara2019-08-121-2/+5
* freedreno: add tiling parameters for 2D/2DArray/3DKhaled Emara2019-08-121-2/+19
* freedreno: simplified slices setup for a3xxKhaled Emara2019-08-121-12/+3
* freedreno: enable tiled textures for debug buildsKhaled Emara2019-08-129-8/+173
* intel/fs: add 64 bit integer multiplication loweringPaulo Zanoni2019-08-122-4/+70
* intel/compiler: invert the logic of lower_integer_multiplication()Paulo Zanoni2019-08-121-13/+10
* intel/compiler: don't instantiate a builder for each instructionPaulo Zanoni2019-08-122-12/+10
* intel/compiler: extract subfunctions of lower_integer_multiplication()Paulo Zanoni2019-08-122-186/+197
* nir: merge and extend nir_opt_move_comparisons and nir_opt_move_load_uboRhys Perry2019-08-129-153/+37
* nir: replace nir_move_load_const() with nir_opt_sink()Rhys Perry2019-08-127-146/+238
* anv/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-124-0/+109
* lima/ppir: Add fddx and fddyAndreas Baierl2019-08-124-0/+60
* radv: Enable VK_KHR_pipeline_executable_properties.Bas Nieuwenhuizen2019-08-122-1/+7
* radv: Implement radv_GetPipelineExecutableStatisticsKHR.Bas Nieuwenhuizen2019-08-121-0/+103
* radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.Bas Nieuwenhuizen2019-08-121-5/+104
* radv: Implement radv_GetPipelineExecutablePropertiesKHR.Bas Nieuwenhuizen2019-08-121-0/+111
* radv: Keep shader info when needed.Bas Nieuwenhuizen2019-08-124-23/+36
* radv: Add VK_KHR_pipeline_executable_properties in disabled state.Bas Nieuwenhuizen2019-08-121-0/+1
* radv: Use string for nir dumping.Bas Nieuwenhuizen2019-08-124-8/+29
* radv: Get max workgroup size without nir.Bas Nieuwenhuizen2019-08-123-19/+28
* radv: Add utility function to calculate max waves.Bas Nieuwenhuizen2019-08-122-8/+24
* iris/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-0/+110
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
* i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-6/+109
* pan/midgard: Handle 64-bit address in mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-121-1/+36
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