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* swr/rast: update SWR rasterizer shader statsAlok Hota2019-02-0510-38/+204
| | | | | | Primarily refactoring internal stats types Reviewed-by: Bruce Cherniak <[email protected]>
* loader/dri3: Use strlen instead of sizeof for creating VRR property atomMichel Dänzer2019-02-051-1/+1
| | | | | | | | | | | sizeof counts the terminating null character as well, so that also contributed to the ID computed for the X11 atom. But the convention is for only the non-null characters to contribute to the atom ID. Fixes: 2e12fe425fe3 "loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property" Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: add missing vec opcodes in lower_bool_to_floatJonathan Marek2019-02-051-0/+6
| | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: release references to image textures when a context is destroyedGert Wollny2019-02-053-0/+15
| | | | | | | | | | | | | When a texture is still bound as an image and the context it was bound in is destroyed but not the texture, then the texture will still hold the resource and will not be freed when it is finally destroyed. Hence, release these references when the context is destroyed. This leak was triggered by virglrenderer: https://gitlab.freedesktop.org/virgl/virglrenderer/issues/86 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release tokens after creating the shader programGert Wollny2019-02-051-0/+2
| | | | | | | | | | | | | | | | | | | | ureg_get_tokens clears the reference to the tokens, and create_compute_state makes a copy, hence the tokens must be explicitely released. Fixes: Direct leak of 256 byte(s) in 1 object(s) allocated from: #0 0x7ff729cf3c60 in realloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdbc60) #1 0x7ff721b1240c in tokens_expand ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:234 #2 0x7ff721b1c9c0 in get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:257 #3 0x7ff721b1c9c0 in copy_instructions ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2040 #4 0x7ff721b1c9c0 in ureg_finalize ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2090 #5 0x7ff721b1e919 in ureg_get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2167 #6 0x7ff721f8b35a in si_create_dma_compute_shader ../../samba/mesa/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c:219 #7 0x7ff722043ed9 in si_compute_do_clear_or_copy ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:156 #8 0x7ff7220448d3 in si_clear_buffer ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:247 #9 0x7ff7220350e8 in vi_dcc_clear_level ../../samba/mesa/src/gallium/drivers/radeonsi/si_clear.c:274 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* isl: assert that Gen8+ don't have bit6_swizzlingCaio Marcelo de Oliveira Filho2019-02-041-0/+3
| | | | | | | v2: Rewrite the condition to more clearly match the comment. (Jordan) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: skip bit6 swizzle detection in Gen8+Caio Marcelo de Oliveira Filho2019-02-041-2/+14
| | | | | | | | It is always false on Gen8+. Also, move the variable definition near its use. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: skip bit6 swizzle detection in Gen8+Caio Marcelo de Oliveira Filho2019-02-041-0/+14
| | | | | | | It is always false on Gen8+. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: keep the phi order when splitting blocksCaio Marcelo de Oliveira Filho2019-02-041-3/+2
| | | | | | | | All things being equal is better to keep the original order. Since the new block is empty, push the phis in order to tail. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* nv50,nvc0: add explicit settings for recent capsIlia Mirkin2019-02-042-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]>
* panfrost: Implement Midgard shader toolchainAlyssa Rosenzweig2019-02-0513-2/+6383
| | | | | | | | | | | | | | | This patch implements the free Midgard shader toolchain: the assembler, the disassembler, and the NIR-based compiler. The assembler is a standalone inaccessible Python script for reference purposes. The disassembler and the compiler are implemented in C, accessible via the standalone `midgard_compiler` binary. Later patches will use these interfaces from the driver for online compilation. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* panfrost: Initial stub for Panfrost driverAlyssa Rosenzweig2019-02-0527-5/+3244
| | | | | | | | | | | | | This patch adds an initial stub for the Gallium driver, containing simple screen functions and the majority of the driver headers but no actual functionality. It further adds the winsys glue for linking in this stub driver via kmsro on Rockchip/Amlogic boards. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* radeonsi: fix crashing performance counters (division by zero)Marek Olšák2019-02-041-1/+1
| | | | Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c"
* radeonsi: handle render_condition_enable in si_compute_clear_render_targetMarek Olšák2019-02-043-3/+8
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* radeonsi: use compute for clear_render_target when possibleSonny Jiang2019-02-045-0/+184
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* st/mesa: Set pipe_image_view::shader_access in PBO readpixels.Kenneth Graunke2019-02-041-0/+1
| | | | | | | | | | | | Commit 8b626a22b24089edf90cb1b06e5b1895bb36c61b introduced a new pipe_image_view::shader_access field, indicating the access mode specified in the shader. st/mesa's built-in PBO download shader creates a write-only image buffer, so we should flag it as such. Nobody uses this field yet (Iris will), so we don't need to backport this fix to stable branches. Reviewed-by: Marek Olšák <[email protected]>
* intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.Rodrigo Vivi2019-02-041-0/+5
| | | | | | | | | | | | | Align with kernel commits: 5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.") 03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake") Cc: José Roberto de Souza <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Fix VK_EXT_transform_feedback working with varyings packed in PSIZDanylo Piliaiev2019-02-041-3/+20
| | | | | | | | | | | | | Transform feedback did not set correct SO_DECL.ComponentMask for varyings packed in VARYING_SLOT_PSIZ: gl_Layer - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z gl_PointSize - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w Fixes: 36ee2fd61c8f94 "anv: Implement the basic form of VK_EXT_transform_feedback" Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: Handle VK_ATTACHMENT_UNUSED in CmdClearAttachmentDanylo Piliaiev2019-02-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | From the Vulkan 1.0.98 spec for vkCmdClearAttachments: "If any attachment to be cleared in the current subpass is VK_ATTACHMENT_UNUSED, then the clear has no effect on that attachment." "If the aspectMask member of any element of pAttachments contains VK_IMAGE_ASPECT_COLOR_BIT, then the colorAttachment member of that element must either refer to a color attachment which is VK_ATTACHMENT_UNUSED, or must be a valid color attachment." "If the aspectMask member of any element of pAttachments contains VK_IMAGE_ASPECT_DEPTH_BIT, then the current subpass' depth/stencil attachment must either be VK_ATTACHMENT_UNUSED, or must have a depth component" "If the aspectMask member of any element of pAttachments contains VK_IMAGE_ASPECT_STENCIL_BIT, then the current subpass' depth/stencil attachment must either be VK_ATTACHMENT_UNUSED, or must have a stencil component" Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Handle VK_ATTACHMENT_UNUSED in colorAttachmentDanylo Piliaiev2019-02-041-0/+4
| | | | | | | | | | | | | From the Vulkan 1.0.98 spec for vkCmdClearAttachments: "If the aspectMask member of any element of pAttachments contains VK_IMAGE_ASPECT_COLOR_BIT, then the colorAttachment member of that element must either refer to a color attachment which is VK_ATTACHMENT_UNUSED, or must be a valid color attachment." Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: don't flush src stages when dstStageMask == BOTTOM_OF_PIPESamuel Pitoiset2019-02-042-3/+19
| | | | | | | Original patch by Fredrik Höglund. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not set preserveAttachments for internal render passesSamuel Pitoiset2019-02-044-18/+18
| | | | | | | We don't use that. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: drop useless checks when resolving subpass color attachmentsSamuel Pitoiset2019-02-042-8/+4
| | | | | | | | | | | The Vulkan spec says: "If pResolveAttachments is not NULL, for each resolve attachment that does not have the value VK_ATTACHMENT_UNUSED, the corresponding color attachment must not have the value VK_ATTACHMENT_UNUSED." Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: execute external subpass barriers after ending subpassesSamuel Pitoiset2019-02-041-2/+2
| | | | | | | | | Outgoing dependencies (ie. external) should happen after the subpass. This doesn't change anything for subpass resolves as we already make sure that attachments are shader readable. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: accumulate all ingoing external dependencies to the first subpassSamuel Pitoiset2019-02-041-0/+4
| | | | | | | In case two or more subpasses declare ingoing external dependencies. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle subpass dependencies correctlySamuel Pitoiset2019-02-041-6/+6
| | | | | | | | | The different masks should be accumulated. For example if two subpasses declare an outgoing dependency (ie. dst == VK_SUBPASS_EXTERNAL). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: track if subpasses have color attachmentsSamuel Pitoiset2019-02-043-9/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_render_pass_add_subpass_dep() helperSamuel Pitoiset2019-02-041-40/+38
| | | | | | | To share common code that handles subpass dependencies. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move some render pass things to radv_render_pass_compile()Samuel Pitoiset2019-02-041-28/+38
| | | | | | | | radv_render_pass_compile() is common to vkCreateRenderPass() and vkCreateRenderPass2(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle final layouts at end of every subpass and render passSamuel Pitoiset2019-02-041-22/+38
| | | | | | | | That shouldn't change anything as we check if the last subpass id is the final subpass. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: determine the last subpass id for every attachmentsSamuel Pitoiset2019-02-042-0/+15
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use the new attachments array when starting subpassesSamuel Pitoiset2019-02-041-12/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the list of attachments for every subpassSamuel Pitoiset2019-02-047-55/+96
| | | | | | | | | This reworks how the depth stencil attachment is used for simplicity. This also introduces radv_render_pass_compile() helper that will be used for further optimizations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move subpass image transitions to radv_cmd_buffer_begin_subpass()Samuel Pitoiset2019-02-045-29/+27
| | | | | | | Instead of doing them in radv_cmd_buffer_set_subpass(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_cmd_buffer_begin_subpass() helperSamuel Pitoiset2019-02-041-12/+32
| | | | | | | | To unify some code in BeginRenderPass() and NextSubpass(). Based on Intel ANV driver. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless MAYBE_UNUSED in CmdBeginRenderPass()Samuel Pitoiset2019-02-041-1/+1
| | | | | | | Trivial. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused radv_render_pass_attachment::view_maskSamuel Pitoiset2019-02-042-11/+0
| | | | | | | Trivial. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: bail out when no image transitions will be performedSamuel Pitoiset2019-02-041-0/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: drop the xcb-xrandr version requirementMarek Olšák2019-02-031-1/+1
| | | | | | | autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04. Cc: 18.3 19.0 <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* wsi/display: add commentEric Engestrom2019-02-021-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Keith Packard <[email protected]>
* relnotes: Add VK_EXT_buffer_device_addressJason Ekstrand2019-02-021-0/+1
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* anv: Implement VK_EXT_buffer_device_addressJason Ekstrand2019-02-015-2/+67
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/fs: Implement nir_intrinsic_global_atomic_*Jason Ekstrand2019-02-018-0/+202
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Use SENDS for A64 writes on gen9+Jason Ekstrand2019-02-011-10/+23
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Implement load/store_global with A64 untyped messagesJason Ekstrand2019-02-017-1/+273
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 modeJason Ekstrand2019-02-011-7/+6
| | | | | | | | | | | Previously, we only applied the fix to shaders with a dispatch mode of SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 instructions. If you have a SIMD8 instruction in a SIMD16 shader, neither would trigger and the restriction could still be hit. Fixes: 232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Properly handle 64-bit types in LOAD_PAYLOADJason Ekstrand2019-02-012-2/+7
| | | | | | | | | By just assigning dst.type to src[i].type, we ensure that the offset at the end of the loop actually offsets it by the right number of registers. Otherwise, we'll get into a case where we copy with a Q type and then offset with a D type and things get out of sync. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/cse: Split create_copy_instr into three casesJason Ekstrand2019-02-011-17/+17
| | | | | | | | | | Previously, we tried to combine all cases where the instruction being CSE'd writes to more than one MOV worth of registers into one case with a bit of special casing for LOAD_PAYLOAD. This commit splits things so that LOAD_PAYLOAD is entirely it's own case. This makes tweaking the LOAD_PAYLOAD case simpler in the next commit. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/nir: Add global support to lower_mem_access_bit_sizesJason Ekstrand2019-02-011-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Fix memory corruption when compiling a CSOscar Blumberg2019-02-011-1/+2
| | | | | | | | Missing check for shader stage in the fs_visitor would corrupt the cs_prog_data.push information and trigger crashes / corruption later when uploading the CS state. Reviewed-by: Kenneth Graunke <[email protected]>
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