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* util: rename timestamp param in disk_cache_create()Timothy Arceri2018-10-031-4/+4
| | | | | | | | Only some drivers use a timestamp here. Others use things such as build-id, or even a combination of build-ids from Mesa and LLVM. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
| | | | | | | | | Fixes GPU hangs. Cc: 18.1 18.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107857 Signed-off-by: Józef Kucia <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i965: Replace checks for rb->Name with FlipY (v2)Fritz Koenig2018-10-022-13/+11
| | | | | | | | | | | | | In the GL_MESA_framebuffer_flip_y implementation _mesa_is_winsys_fbo checks were replaced with FlipY checks. rb->Name is also used to determine if a buffer is winsys. v2: Fixes annotation [for emil] Fixes: ab05dd183cc ("i965: implement GL_MESA_framebuffer_flip_y [v3]") Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
| | | | | so that it's not NULL when loading radeonsi and a GCN GPU is not present in the system.
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
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* spirv: Move function call handling to vtn_cfgJason Ekstrand2018-10-023-63/+65
| | | | | | | It makes way more sense for it to live there with the rest of function handling. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/from_ssa: Don't rewrite derefs destinations to registersJason Ekstrand2018-10-021-0/+6
| | | | | | | | | | | | We already call nir_rematerialize_derefs_in_use_blocks_impl prior to calling nir_lower_ssa_defs_to_regs_block so the assertion that all deref uses in the block should hold. This fixes the following CTS test when SPIR-V optimization recipe 1: dEQP-VK.glsl.struct.local.loop_nested_struct_array_vertex Fixes: 606eb56ab9449b "intel/nir: Only lower load/store derefs" Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/cf: Remove phi sources if needed in nir_handle_add_jumpJason Ekstrand2018-10-021-17/+21
| | | | | | | | | | | | If the block in which the jump is inserted is the predecessor of a phi then we need to remove phi sources otherwise the phi may end up with things improperly connected. This fixes the following CTS test when dEQP is run with SPIR-V optimization recipe 1: dEQP-VK.glsl.functions.control_flow.return_in_nested_loop_vertex Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: suppress warning about unhandled image layoutEric Engestrom2018-10-021-0/+3
| | | | | | | | | Let's just be explicit that VK_NV_shading_rate_image is not supported. Suggested-by: Jason Ekstrand <[email protected]> Fixes: 6ee17091708a41c4aa81a "vulkan: Update the XML and headers to 1.1.86" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/a6xx: hwbinningRob Clark2018-10-028-105/+159
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-10-027-41/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* intel/fs: Fix a typo in need_matching_subreg_offsetJason Ekstrand2018-10-021-1/+1
| | | | | | | | | This fixes a bunch of Vulkan subgroup tests on little core platforms. Fixes: 4150920b95 "intel/fs: Add a helper for emitting scan operations" Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* util: disable cache if we have no build-id and timestamp is zeroTimothy Arceri2018-10-022-4/+9
| | | | | | | | | | Timestamp can be zero for example when Flatpak is used. In this case just disable the cache rather then segfaulting when incompatible cache items are loaded. V2: actually return false when mtime is 0. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* include: sync eglext.h from KhronosEric Engestrom2018-10-021-5/+81
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Tapani Pälli <[email protected]>
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
| | | | | | | | | | | | | | | This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue to have this problem. It fixes rendering issues in some menu and loading screens of Civ VI which can be seen in the trace from bug 104602. Note: This does not fix the black triangles on Vega for bug 104602. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
* anv: Implement VK_KHR_driver_propertiesJason Ekstrand2018-10-012-0/+24
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Update the XML and headers to 1.1.86Jason Ekstrand2018-10-012-69/+1433
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not try to set DCC_CONTROL when image doesn't use DCCSamuel Pitoiset2018-10-011-1/+1
| | | | | | | | Unnecessary. While we are at it, remove the check for pre-VI because it's already checked earlier. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add a sanity check for mutable formats and TC-compat HTILESamuel Pitoiset2018-10-011-5/+22
| | | | | | | | | | If apps use the MUTABLE bit and the same formats as the image one in the list, we can still enable TC-compat HTILE. I don't think this happens often but given the fact that TC-compat HTILE allows a nice boost in some situations, it's worth checking. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disable HTILE for very small depth surfacesSamuel Pitoiset2018-10-011-1/+3
| | | | | | | | | | | Like we disable DCC/CMASK for small color surfaces as well. Serious Sam 2017 creates a 1x1 depth surface and I think it should be faster to do slow clears on the graphics queue instead of fast clears on compute, and eventually a depth expand if the surface isn't TC-compatible HTILE. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add potential missing fields for DB_EQAASamuel Pitoiset2018-10-011-1/+3
| | | | | | | Other drivers set these two as well, just apply the same rule. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disable complicated point clipping against user clip planesSamuel Pitoiset2018-10-011-1/+0
| | | | | | | | | I don't think this is required by Vulkan too. Ported from RadeonSI (AMDVLK doesn't set it either). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: Clarify comment in util_init_thread_pinningMichel Dänzer2018-09-281-1/+4
| | | | | | | | | | As discussed in the review of the patch which added the comment: Nothing happens when a thread is created, because pthread_atfork doesn't affect creating threads. However, spawning a child process will likely crash. Reviewed-by: Marek Olšák <[email protected]>
* radv: do not sync CP DMA when copying buffersSamuel Pitoiset2018-09-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already track if the DMA engine is busy/idle with a flag, and we emit a packet that waits for all CP DMA operations to be complete. This is done at end of command buffer because the kernel doesn't wait for them, and also when emitting barriers, so it should be safe. This improves small copies for both aligned and unaligned sizes. Aligned sizes: BEFORE: 1 KB: 59.840000 ms 2 KB: 71.200000 ms AFTER: 1 KB: 31.200000 ms 2 KB: 31.040000 ms Unaligned sizes: BEFORE: 2 KB: 68.3200 ms 3 KB: 79.3600 ms 5 KB: 76.6400 ms 9 KB: 90.8800 ms 17 KB: 116.0000 ms AFTER: 2 KB: 31.0400 ms 3 KB: 32.0000 ms 5 KB: 30.8800 ms 9 KB: 30.5600 ms 17 KB: 29.6000 ms Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: adjust the CmdUpdateBuffer threshold for optimal performanceSamuel Pitoiset2018-09-282-1/+3
| | | | | | | | | | | | | | | | According to my benchmark results, it appears that we should reduce the threshold to 1024. BEFORE: 1 KB: 68.656000 ms 2 KB: 118.368000 ms AFTER: 1 KB: 31.760000 ms 2 KB: 29.840000 ms Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not use the availability bit for timestamp queriesSamuel Pitoiset2018-09-282-30/+28
| | | | | | | | | | | It's unnecessary because we can just check if the timestamp is to different to the default value when a pool is created or resetted. Instead of waiting for the availability bit to be 1, we have to emit a not equal WAIT_REG_MEM for checking if the timestamp is ready. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
| | | | | | | | Pulling this logic out means we can share the logic and avoid a couple of temporary variables that helped make things clearer before. Note that in either vismode case, we always program vismode 0. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
| | | | | | | | Now that we've copied the emit logic into each branch of the if (info->index_size) statement, we can simplify the logic a bit according to which case we're in. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
| | | | | | | This splits the two code paths into separate functions and moves the "if (info->indirect)" test into draw_impl(). Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Inline fd6_draw()Kristian H. Kristensen2018-09-271-31/+17
| | | | | | Simplify the code a bit by inlining this helper. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move emit_marker and wfi to draw_impl()Kristian H. Kristensen2018-09-271-17/+12
| | | | | | | This way the markers clearly bracket the draw call and isn't duplicated for both direct and indirect draw code. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move inline functions out of fd6_draw.hKristian H. Kristensen2018-09-273-108/+110
| | | | | | Only used in fd6_draw.c so put them there. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: fix a typo in launch_gridHyunjun Ko2018-09-271-1/+1
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* freedreno/ir3: fix the param order of cmpxchgHyunjun Ko2018-09-271-2/+2
| | | | | | | | | | | According to the following definition, int AtomicCompSwap(inout int mem, uint compare, uint data); the preceding one in atomic_comp_swap of NIR is compare and data is followed, while src0 for cmpxchg needs vec2(data, compare) So for ssbo/image deref comp_swap, that should be reversed. Fixes: dEQP-GLES31.functional.image_load_store.*.atomic.comp_swap*
* freedreno/a6xx: fix shaders w/ >= 24 regsRob Clark2018-09-271-1/+1
| | | | | | | | Possibly these bits mean something else now. Blob always seems to use FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads to overlap registers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gl_FragCoord.wRob Clark2018-09-271-2/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: handle invalidated buffers harderRob Clark2018-09-278-7/+39
| | | | | | Do a better job of skipping mem2gmem/gmem2mem.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix constlenRob Clark2018-09-271-7/+6
| | | | | | | | | Fix a few bits of confusion, as with previous gen's constlen is aligned to 4, and value in bitfield is left-shifted by 2 (ie. divided by 4). But this is done by the CONSTLEN() accessor/builder fxn, so don't do it twice. Also HLSQ_FS_CNTL.CONSTLEN is not special. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix inorder rendering caseRob Clark2018-09-271-6/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: backface stencil stateRob Clark2018-09-272-2/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gpu crash with separate-stencilRob Clark2018-09-271-1/+1
| | | | | | | Fixes a crash in (of all things) dEQP-GLES2.info.vendor with --deqp-surface-type=fbo.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix MRT configRob Clark2018-09-271-7/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix potential hang when destroying batchRob Clark2018-09-271-1/+1
| | | | | | | batch_flush_reset_dependencies() expects to be called unlocked, and can call fd_batch_reference() which can try to aquire the screen lock again. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix corrupted fb stateRob Clark2018-09-272-2/+5
| | | | | | | | | | | In c3d9f29b we allowed ctx->batch to be null, and started tracking the current framebuffer state in fd_context. But the existing logic in fd_blitter_pipe_begin() would, if !ctx->batch, set null fb state to be restored after blit. Which broke the world of deqp (and probably other things) Fixes: c3d9f29b781 freedreno: allocate ctx's batch on demand Signed-off-by: Rob Clark <[email protected]>
* freedreno: simplify pctx->clear()Rob Clark2018-09-276-74/+11
| | | | | | | | | | | | This is defined to always clear the entire surface(s) specified, regardless of scissor state.. mesa/st will turn scissored clears into a draw. So rip about a bunch of unnecessary machinery. Also remove a comment that was obsolete since using u_blitter to turn clear into draw (for the cases where there isn't a hw blitter fast-path). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix FD_MESA_DEBUG=flushRob Clark2018-09-272-2/+8
| | | | | | | The logic to force a flush every draw was short-circuited with newer kernels. Also it should apply to clears as well. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix scissor state emitRob Clark2018-09-274-4/+8
| | | | | | | The effective scissor changes based on rasterizer->scissor flag, so we need to re-emit scissor state when rasterizer state changes. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-09-278-340/+1089
| | | | Signed-off-by: Rob Clark <[email protected]>
* st/mesa: do not call update_framebuffer_size with NULL pointerErik Faye-Lund2018-09-271-1/+2
| | | | | | | | | | | | | | | | In st_renderbuffer_alloc_storage, we avoid allocating storage for zero-sized buffers, leading to this pointer being NULL. We already take care to avoid dereferencing these pointers for color-buffers, but not for depth/stencil-buffers. So let's thread a bit more carefully here. This avoids a crash while running Piglit's glx/glx-visuals-stencil test, both on virgl and r600g. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Guillaume Charifi <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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