summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* winsys/radeon: fix nop packet padding for hawaiiAndreas Boll2014-08-123-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial firmware for hawaii does not support type3 nop packet. Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2. If the returned value is 3, then the new firmware is used. This patch uses type2 for the old firmware and type3 for the new firmware. It fixes the cases when the old firmware is used and the user wants to manually enable acceleration. The two possible scenarios are: - the kernel has no support for the new firmware. - the kernel has support for the new firmware but only the old firmware is available. Additionaly this patch disables GPU acceleration on hawaii if the kernel returns a value < 2. In this case the kernel hasn't the required fixes for proper acceleration. v2: - Fix indentation - Use private struct radeon_drm_winsys instead of public struct radeon_info - Rename r600_accel_working2 to accel_working2 v3: - Use type2 nop packet for returned value < 3 v4: - Fail to initialize winsys for returned value < 2 Cc: [email protected] Cc: Alex Deucher <[email protected]> Cc: Jérôme Glisse <[email protected]> Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Andreas Boll <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* mesa: regenerate gl_mangle.hBrian Paul2014-08-121-0/+139
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: update wglext.h to version 20140810Brian Paul2014-08-121-2/+9
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: update glxext.h to version 20140810Brian Paul2014-08-121-2/+9
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: update glext.h to version 20140810Brian Paul2014-08-121-2/+378
| | | | | | This brings in the new OpenGL 4.5 features. Reviewed-by: Ilia Mirkin <[email protected]>
* svga: Add a limit to the maximum surface sizeCharmaine Lee2014-08-129-7/+130
| | | | | | | | | This patch adds a limit to the maximum surface size which is based on the maximum size of a single mob. If this value is not available, the maximum surface size is by default set to 128 MB. Reviewed-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/st: Move declaration to top of block.José Fonseca2014-08-121-1/+3
| | | | | | To fix MSVC build failure. Trivial.
* mesa/st: add support for dynamic sampler offsetsIlia Mirkin2014-08-122-18/+43
| | | | | | | | | | | | | | Replace the plain sampler index with a register reference to a sampler. We also need to keep track of the sampler array size when there is a relative reference so that we can mark the whole array used. To facilitate implementation, we add a separate ADDR register that exclusively handles the sampler relative address. Other approaches would be more invasive. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/uvd: fix gpu_address for video surfacesChristian König2014-08-122-0/+4
| | | | | | | | | | | We need to get the new gpu_address as well when reallocating the cs buffer. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=82428 Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Kai Wasserbäch <[email protected]>
* mesa: Add a new function for getting the nonconst sampler array indexChris Forbes2014-08-122-0/+14
| | | | | | | | | | | | | If the array index is not a constant expression, the existing support will assume a zero offset (giving us the sampler index of the base of the array). For dynamically uniform indexing of sampler arrays, we need both that and the indexing expression. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: Allow dynamically uniform sampler array indexing with 4.0/gs5Chris Forbes2014-08-121-1/+8
| | | | | | | | | V2: Expand comment to explain what dynamically uniform expressions are about. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: describe the tex arguments for fermi/keplerIlia Mirkin2014-08-111-0/+25
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add kepler+ support for indirect texture referencesIlia Mirkin2014-08-111-7/+27
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add base tex offset for fermi indirect tex caseIlia Mirkin2014-08-111-2/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* i965: Revert part of f5cc3fdcf1680b116612fac7c39f1bd79f5e555e.Kenneth Graunke2014-08-111-1/+1
| | | | | | Fixes non-termination in various Piglit tests. Reviewed-by: Jason Ekstrand <[email protected]>
* vc4: Flip which primitives are considered front-facing.Eric Anholt2014-08-111-1/+1
| | | | This mostly fixes glxgears rendering.
* vc4: Don't forget to set the depth clear value in the packet.Eric Anholt2014-08-111-1/+1
| | | | This gets glxgears partially rendering again.
* vc4: Add support for gl_FragCoord.Eric Anholt2014-08-115-4/+76
| | | | | | | This isn't passing all tests (glsl-fs-fragcoord-zw-ortho, for example), but it does get a bunch more tests passing. v2: Rebase on helpers change.
* vc4: Refactor shader input setup again.Eric Anholt2014-08-111-17/+24
| | | | This makes some space for handling special inputs like fragcoords.
* vc4: Clean up the tile alloc buffer size.Eric Anholt2014-08-111-1/+9
| | | | | | | This prevents some simulator assertion failures, but it does mean (since I've dropped the "* 16" padding) that on real hardware you need a kernel that does overflow memory management (currently, "drm/vc4: Add support for binner overflow memory allocation." in my kernel tree).
* vc4: Clarify some values implicitly chosen for binning config.Eric Anholt2014-08-111-1/+4
| | | | These #defines are 0, but it should help make math above make more sense.
* vc4: Improve simulator memory allocation.Eric Anholt2014-08-111-4/+20
| | | | This should reduce a bunch of spurious failures in sim.
* vc4: Handle stride==0 in VBO validationEric Anholt2014-08-111-7/+9
|
* vc4: Stash some debug code for looking at what BOs are at what hindex.Eric Anholt2014-08-112-0/+5
| | | | When you're debugging validation, it's nice to know what the BOs are for.
* vc4: Use GEM under simulation even for non-winsys BOs.Eric Anholt2014-08-112-14/+9
| | | | | | | In addition to reducing sim-specific code, it also avoids our local handle allocation conflicting with the host GEM's handle numbering, which was causing vc4_gem_hindex() to not distinguish between winsys BOs and the same-numbered non-winsys bo.
* vc4: Don't forget to unmap the GEM BO when freeing.Eric Anholt2014-08-111-0/+3
| | | | Otherwise it'll stick around forever.
* vc4: Add validation of raster-format textures.Eric Anholt2014-08-112-17/+96
| | | | | | ... and reject everything else, for now. v2: Rebase on v2 of the rendering config validation change.
* vc4: Drop VC4_PACKET_PRIMITIVE_LIST_FORMAT.Eric Anholt2014-08-112-4/+4
| | | | | | It's not relevant to our command streams any more. v2: Fix indentation and a typo in the comment.
* vc4: Add validation that vertex indices don't overflow VBO bounds.Eric Anholt2014-08-112-18/+71
|
* vc4: Fix the shader record size for extended strides.Eric Anholt2014-08-111-0/+1
| | | | | It turns out they aren't packed when attributes are missing, according to both docs and simulation.
* vc4: Fix the shader record size for extended strides.Eric Anholt2014-08-111-1/+4
| | | | | | | It turns out they aren't packed when attributes are missing, according to both docs and simulation. v2: Drop unused variable.
* vc4: Add a bunch of validation of render mode configuration.Eric Anholt2014-08-113-11/+151
| | | | v2: Fix a build break after some previous rebase.
* vc4: Store the (currently always linear) tiling format in the resource.Eric Anholt2014-08-114-8/+25
|
* vc4: Add a bunch of validation of the binning mode config.Eric Anholt2014-08-112-17/+140
|
* vc4: Validate that the same BO doesn't get reused for different purposes.Eric Anholt2014-08-113-37/+81
| | | | | | | | | We don't care if things like vertex data get smashed by render target data, but we do need to make sure that shader code doesn't get rendered to. v2: Fix overflowing read of gl_relocs[] that incorrect flagged of some VBOs as shader code.
* vc4: Use the packet #defines in the kernel validation code.Eric Anholt2014-08-111-45/+40
|
* vc4: Rename GEM_HANDLES to be in a namespace.Eric Anholt2014-08-112-2/+8
| | | | | It's not a real VC4 hardware packet, but I've put in a comment to explain it.
* vc4: Clean up TMU write validation.Eric Anholt2014-08-111-77/+64
| | | | | | The comment conflicted with the support in the code, so I moved the TMU write validation to where the comment was, and dropped some dead arguments from the functions while changing their signatures.
* vc4: Update a comment about shader validationEric Anholt2014-08-111-4/+2
|
* vc4: Add proper translation from Zc to Zs for vertex output.Eric Anholt2014-08-112-1/+18
| | | | This fixes the remaining failure in depthfunc.
* vc4: Add support for depth clears and tests within a tile.Eric Anholt2014-08-1110-12/+65
| | | | | | | | | This doesn't load/store the Z contents across submits yet. It also disables early Z, since it's going to require tracking of Z functions across multiple state updates to track the early Z direction and whether it can be used. v2: Move the key setup to before the search for the key.
* vc4: Avoid flushing when mapping buffers that aren't in the batch.Eric Anholt2014-08-113-1/+50
| | | | | This should prevent a bunch of unnecessary flushes for things like updating immediate vertex data.
* vc4: Drop the flush at the end of the drawEric Anholt2014-08-112-2/+2
| | | | Now we actally get multiple draw calls per submit.
* vc4: Align following shader recs to 16 bytes.Eric Anholt2014-08-112-2/+10
| | | | | Otherwise, the low address bits will end up being interpreted as attribute counts.
* vc4: Fix a potential src buffer overflow in shader rec validation.Eric Anholt2014-08-111-0/+1
|
* vc4: Keep a reference to BOs queued for rendering.Eric Anholt2014-08-113-8/+4
| | | | | | Otherwise, once we're not flushing at the end of every draw, we'll free things like gallium resources, and free the backing GEM object, before we've flushed the rendering using it to the kernel.
* vc4: Compute the proper end address of the relocated command lists.Eric Anholt2014-08-112-2/+5
| | | | | | | | | render_cl_size/bin_cl_size includes relocations, while the hardware buffer doesn't. If you don't emit a HALT packet, the command parser continues until the end register's value. We can't allow executing unvalidated buffer contents (and it's actually harmful in the render lists Mesa is emitting, since VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF doesn't trigger a halt).
* vc4: Walk tiles horizontally, then vertically.Eric Anholt2014-08-111-2/+2
| | | | | I was confused looking at my addresses in dumps because I was seeing the tile branch offsets jumping all over.
* vc4: Track clears veresus uncleared draws, and the clear color.Eric Anholt2014-08-113-34/+117
| | | | | | This is a step toward queueing more than one draw per frame. Fixes piglit attribute0 test, since we get a working clear color now.
* vc4: Move the rest of RCL setup to flush time.Eric Anholt2014-08-112-33/+30
| | | | | We only want to set up render target config and clear colors once per frame.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 03:47:44 +0000