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* glsl: don't run the GLSL pre-processor when we are skipping compilationTimothy Arceri2017-04-152-9/+20
* glsl: delay optimisations on individual shaders when cache is availableTimothy Arceri2017-04-154-78/+96
* anv: Add the pci_id into the shader cache UUIDJason Ekstrand2017-04-141-5/+15
* etnaviv: native fence fd supportPhilipp Zabel2017-04-157-7/+83
* docs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+Francisco Jerez2017-04-142-4/+7
* i965: enable OpenGL 4.2 in IvybridgeJuan A. Suarez Romero2017-04-142-2/+2
* i965: enable ARB_shader_precision in gen7+Samuel Iglesias Gonsálvez2017-04-141-1/+1
* i965: enable ARB_vertex_attrib_64bit for gen7+Juan A. Suarez Romero2017-04-141-1/+1
* swr: Fix swr osmesa buildGeorge Kyriazis2017-04-141-1/+1
* etnaviv: SINGLE_BUFFER support on GC3000Wladimir J. van der Laan2017-04-158-28/+63
* etnaviv: Update includes from rnndbWladimir J. van der Laan2017-04-155-20/+91
* etnaviv: Add chipMinorFeatures4 and 5Wladimir J. van der Laan2017-04-152-1/+15
* etnaviv: resolve tile status when flushing resourcePhilipp Zabel2017-04-152-0/+11
* etnaviv: stop repeatedly resolving an unchanged resource into its scanout pri...Philipp Zabel2017-04-151-1/+4
* swr: Add polygon stipple supportGeorge Kyriazis2017-04-145-9/+84
* docs/relnotes: add GL_ARB_gpu_shader_fp64 support on i965/ivybridgeSamuel Iglesias Gonsálvez2017-04-141-0/+1
* docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+Samuel Iglesias Gonsálvez2017-04-141-2/+2
* i965: enable OpenGL 4.0 to Ivybridge/BaytrailSamuel Iglesias Gonsálvez2017-04-142-5/+6
* i965: enable ARB_gpu_shader_fp64 for Ivybridge/BaytrailSamuel Iglesias Gonsálvez2017-04-141-1/+1
* i965: Use correct VertStride on align16 instructions.Matt Turner2017-04-141-10/+34
* i965/vec4/dce: improve track of partial flag register writesSamuel Iglesias Gonsálvez2017-04-141-1/+1
* i965/vec4: don't do horizontal stride on some register file typesSamuel Iglesias Gonsálvez2017-04-141-2/+5
* i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.Matt Turner2017-04-141-4/+12
* i965/vec4: use vec4_builder to emit instructions in setup_imm_df()Samuel Iglesias Gonsálvez2017-04-142-50/+50
* i965/vec4: consider subregister offset in live variablesJuan A. Suarez Romero2017-04-141-2/+2
* i965/vec4: fix assert to detect SIMD lowered DF instructions in IVBFrancisco Jerez2017-04-141-5/+1
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-147-27/+60
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-142-8/+1
* i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYTJuan A. Suarez Romero2017-04-141-7/+19
* i965/vec4: keep original type when dealing with null registersJuan A. Suarez Romero2017-04-141-0/+2
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-143-1/+53
* i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-0/+9
* i965/fs: Get 64-bit indirect moves working on IVB.Francisco Jerez2017-04-141-2/+25
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-142-13/+28
* i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECTJuan A. Suarez Romero2017-04-141-3/+14
* i965/fs: fix dst stride in IVB/BYT type conversionsJuan A. Suarez Romero2017-04-141-27/+41
* i965/fs: rename lower_d2x to lower_conversionsSamuel Iglesias Gonsálvez2017-04-144-4/+4
* Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."Samuel Iglesias Gonsálvez2017-04-141-2/+0
* i965/fs: generalize the legalization d2x passSamuel Iglesias Gonsálvez2017-04-142-37/+67
* i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.Matt Turner2017-04-141-0/+13
* i965/fs: clamp exec_size when an instruction has a scalar DF sourceSamuel Iglesias Gonsálvez2017-04-141-3/+8
* i965/fs: double regioning parameters and execsize for DF in IVB/BYTJuan A. Suarez Romero2017-04-141-7/+43
* i965/fs: add helper to retrieve instruction execution typeJuan A. Suarez Romero2017-04-143-5/+64
* i965: Handle IVB DF differences in the validator.Matt Turner2017-04-141-0/+24
* i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga2017-04-141-3/+3
* nir: Destination component count of shader_clock intrinsic is 2Boyan Ding2017-04-142-2/+3
* radeonsi: add missing initialization for userptr buffersNicolai Hähnle2017-04-141-0/+4
* radv: remove the temp descriptor set infrastructureFredrik Höglund2017-04-142-76/+28
* radv: use push descriptors in metaFredrik Höglund2017-04-146-416/+301
* radv: add private push descriptors for metaFredrik Höglund2017-04-142-0/+41
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