summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* i965: Add support for ARGB2101010 rendering.Eric Anholt2011-11-221-1/+1
| | | | | | | | | | | | GL 3.0 specifies GL_RGB10_A2 as a required sized format for rendering and texturing. This introduces two piglit regressions: one due to fbo-mipmap-copypix hitting swrast GetRow (we want to convert swrast to MapRenderbuffer), and one due to fbo-blending-formats being too picky while leaving dithering on. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for RGBA_16 unorm rendering.Eric Anholt2011-11-221-1/+1
| | | | | | | GL 3.0 specifies GL_RGBA16 as a required sized format for rendering and texturing. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for half-float formats.Eric Anholt2011-11-221-7/+11
| | | | | | | | | | | | | | | Now that all the rest of the driver is driven off of the surface formats table, all we really need to do is add the mapping from MESA_FORMAT to BRW_SURFACEFORMAT. However, we also add format override for I16/L16 render targets at the same time, so that existing users of I16 that were getting promoted to I32 and then getting the I32->R32 override still get FBO support. Fixes failures in piglit gl-3.0-required-sized-texture-formats, and will prevent regressions in ARB_texture_float on gen4 when moving to fully table-driven texture format setup. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Fix unpack for MESA_FORMAT_INTENSITY_FLOAT16.Eric Anholt2011-11-221-1/+1
| | | | | | Fixes failures in i965 on fbo-blending-formats when the format is enabled. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Fall back to float16 if float32 isn't supported in ChooseTexFormat.Eric Anholt2011-11-221-0/+11
| | | | | | | Until GL 3.0, there isn't any requirement on the actual sizes of channels chosen. By falling back to 16 here, we can correctly support ARB_texture_float on original i965 hardware, which can't correctly filter 32-bit floats.
* mesa: Add fallback from RGB_FLOAT16 to RGBA_FLOAT16 before RGBA_FLOAT32.Eric Anholt2011-11-221-0/+1
| | | | | | | Not all i965 hardware can do RGB float16, and this will at least save half the memory and have expected behavior in terms of precision. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reorganize MESA_FORMAT -> BRW_SURFACEFORMAT table.Eric Anholt2011-11-221-48/+146
| | | | | | | | | | | | This should be a no-op change. The initializers are reordered to match the ordering of the enum, since there isn't a clearly sensible ordering, but "the order they were added to the driver, sort of" is definitely not one. Also, the unsupported formats are explicitly initialized to 0, so it's more obvious what we aren't claiming to support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Mark texture formats as supported using the surface formats table.Eric Anholt2011-11-221-1/+12
| | | | | | | | This is currently duplicated with intel_context.c's setup of the formats table, and sets true for exactly the same set of formats on gen6. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Improve debug output for begin/finish render texture.Eric Anholt2011-11-221-4/+4
| | | | | | | I've never seen a use for the thread ID value, but knowing the format being rendered is kind of a big deal. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Remove duplicate test for texture attachment completeness.Eric Anholt2011-11-221-8/+0
| | | | | | | | | | | We are already testing this if appropriate in intel_validate_framebuffer (FBO completeness), so no need to avoid attaching the texture to the renderbuffer here. This causes MESA_FORMAT_R11_G11_B10_FLOAT to now be renderable as a texture attachment on i965. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't require spans (swrast) support to consider a format FBO complete.Eric Anholt2011-11-221-3/+10
| | | | | | | | | | | We don't want to go writing GetRow/PutRow for every format required by GL 3.0, when it's very hard to get those functions called, and in every case we want to make swrast do direct mapping through MapRenderbuffer anyway. This causes MESA_FORMAT_R11_G11_B10_FLOAT to be considered complete on gen6. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the surface format table to determine render target supportedness.Eric Anholt2011-11-224-60/+95
| | | | | | | | | | | | | This moves any chipset-dependent logic we want for render target format choices to init time as well. There is still logic left at state update for SRGB handling, where format choices change based on GL state. The brw_render_target_supported() function should now return correct results, instead of relying on the limited results from intel_span_supports_format() to avoid lying about FBO completeness. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add the context to the render_target_supported() vtbl method.Eric Anholt2011-11-227-8/+10
| | | | | | | We're going to want to provide different answers per chipset generation. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add a table of the surface format information from the PRM.Eric Anholt2011-11-221-0/+204
| | | | | | | | | This will be used to drive chosing formats and determining framebuffer completeness, instead of the bunch of ad-hoc checks we have had until now. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Ian Romanick <[email protected]>
* mesa: Make formats.c "datatype" values match glGetTexLevelParameter return.Eric Anholt2011-11-223-9/+14
| | | | | | | | | | | | | | | | | The formats.c code's "datatype" value is "what does this value mean", i.e. unorm or snorm or float, and is the return value from the GL_TEXTURE_RED_TYPE class of queries. The depth formats were marked as GL_UNSIGNED_INT, which is what we use for integer, and not what we should be returning from the glGetTexLevelParameter. In texstore, we were inappropriately using it as an argument to _mesa_unpack_depth_span() that was expecting a value like GL_UNSIGNED_INT or GL_UNSIGNED_SHORT. Just hardcode _mesa_unpack_depth_span()'s arguments for now, though it looks like the consumers of that interface would be happier with using MESA_FORMAT. Reviewed-by: Brian Paul <[email protected]>
* mesa: Don't report types for 0-sized components of textures.Eric Anholt2011-11-221-50/+69
| | | | | | | | | | | | | | | | | | | | The GL_TEXTURE_WHATEVER_SIZE entrypoints were checking if the specified base type of the texture allowed that channel to be present before reporting the size of the channel, so that GL_RGB didn't end up with an alpha size if the hardware driver had to store it that way. The GL_TEXTURE_WHATEVER_TYPE entrypoints weren't checking it, so you would end up with strange responses from the GL involving 0-bit floating-point alpha components in GL_RGB32F, even though it says GL_NONE as expected for other 0-sized channels. Make _TYPE check _BaseFormat the same as _SIZE, which results in fixing most of the GL_RGB* testcases of gl-3.0-required-sized-formats pass on i965. v2: Add a default case with a warning (suggestion by Brian Paul) Reviewed-by: Brian Paul <[email protected]> (v1)
* r600g: handle all remaining CAPsMarek Olšák2011-11-221-0/+6
|
* r600g: remove default case statements in get_paramMarek Olšák2011-11-221-9/+3
| | | | This will throw a compile warning if there's an unhandled CAP.
* r300g: re-order shaders CAPsMarek Olšák2011-11-221-7/+6
|
* r300g: handle SHADER_CAP_OUTPUT_READMarek Olšák2011-11-221-0/+2
|
* r300g: remove default case statements in get_paramMarek Olšák2011-11-221-8/+2
| | | | This will throw a compile warning if there's an unhandled CAP.
* u_vbuf_mgr: rename to u_vbufMarek Olšák2011-11-227-30/+30
|
* u_vbuf_mgr: better way to find a free VB slot + check errors earlyMarek Olšák2011-11-221-41/+62
|
* u_vbuf_mgr: remove a useless variableMarek Olšák2011-11-221-4/+4
|
* u_vbuf_mgr: remove redundant memsetMarek Olšák2011-11-221-3/+1
|
* u_vbuf_mgr: don't reference non-native vertex buffers as nativeMarek Olšák2011-11-221-1/+2
| | | | | also don't mark them as 'user', because they will be uploaded through the translate fallback anyway.
* u_vbuf_mgr: rename translate_vb_slot -> fallback_vb_slotMarek Olšák2011-11-221-15/+14
|
* gallium: separate out floating-point CAPs into its own enumMarek Olšák2011-11-2222-130/+157
| | | | | | | | | | | | | | | The motivation behind this is to add some self-documentation in the code about how each CAP can be used. The idea is: - enum pipe_cap is only valid in get_param - enum pipe_capf is only valid in get_paramf Which CAPs are floating-point have been determined based on how everybody except svga implemented the functions. svga have been modified to match all the other drivers. Besides that, the floating-point CAPs are now prefixed with PIPE_CAPF_.
* gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionallyMarek Olšák2011-11-2215-52/+12
| | | | | Only i965g does not enable GLSL, but that driver has been unmaintained and bitrotting for quite a while anyway.
* glsl: convervative_depth is not allowed in the vertex shaderMarek Olšák2011-11-221-2/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: finish up ARB_conservative_depth (v2)Marek Olšák2011-11-223-4/+16
| | | | | | | v2: updated an error message Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: rename the AMD_conservative_depth extension flag to ARBMarek Olšák2011-11-224-6/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: quick fix of CopyPixels with GL_DEPTH_STENCILMarek Olšák2011-11-221-0/+7
| | | | | | | | This fixes: - depthstencil-default_fb-copypixels - fbo-depthstencil-GL_DEPTH24_STENCIL8-copypixels Reviewed-by: Brian Paul <[email protected]>
* linker: Remove erroneous multiply by 4 in uniform usage calculationIan Romanick2011-11-221-5/+5
| | | | | | | | | | | | | | | The old count_uniform_size::num_shader_uniforms was actually calculating the number of components used. Multiplying by 4 when setting gl_shader::num_uniform_components caused us to count 4x as many uniform components as were actually used. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42930 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42966 Acked-by: Marek Olšák <[email protected]> Tested-by: Vinson Lee <[email protected]> Tested-by: Pavel Ondračka <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesaChad Versace2011-11-2242-792/+2130
|\
| * i965/gen6: Enable HiZ by defaultChad Versace2011-11-221-6/+2
| | | | | | | | | | | | | | | | | | | | Regresses one Piglit test: bugs/fdo10370. I'm not enabling HiZ for gen7 yet because it causes a mysterious performance regression. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Use separate stencil whenever possibleChad Versace2011-11-222-2/+2
| | | | | | | | | | | | | | | | | | For depthstencil renderbuffers, we were using separate stencil only if the hardware required it. Since the performance gains from HiZ is so high, we should always use separate stencil if the hardware supports it. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965: Implement the actual tables for texture alignment units [v2]Kenneth Graunke2011-11-223-13/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I implemented functions for horizontal/vertical alignment units separately because I find it easier to read that way...especially with all the corner-cases. [chad] Corrected the vertical alignment calculation by checking for depthstencil formats. v2: - Fix typos in intel_horizontal_texture_alignment_unit(): s/height/width/ and s/VALIGN/HALIGN. - Remove special case for compressed formats in intel_get_texture_alignment unit(). Compressed formats are already handled in the halign and valign functions. - Replace check ``_mesa_is_depth_format(...) || _mesa_is_depthstencil_format(...)`` with explcitit checks against GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965/gen6: Set vertical alignment in SURFACE_STATE batchChad Versace2011-11-222-6/+11
| | | | | | | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Store miptree alignment units in the miptreeChad Versace2011-11-224-32/+26
| | | | | | | | | | | | | | | | | | This allows us to replace all the calls to intel_get_texture_alignment_unit() with a single call at miptree creation. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Enable HiZ for texture renderbuffersChad Versace2011-11-221-0/+7
| | | | | | | | | | | | | | | | When a depth texture is first attached to framebuffer, allocate a HiZ miptree for it. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Resolve buffers in intel_map_renderbuffer()Chad Versace2011-11-221-0/+5
| | | | | | | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Resolve buffers in intel_map_texture_image()Chad Versace2011-11-221-0/+5
| | | | | | | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Mark needed resolves when first enabling HiZ on a miptreeChad Versace2011-11-221-1/+20
| | | | | | | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965: Mark that depth buffer needs depth resolve after drawingChad Versace2011-11-221-0/+23
| | | | | | | | | | | | | | | | | | After brw_try_draw_prims() emits a batch, mark that the depth buffer needs a depth resolve if the buffer was written to and if it has an accompanying HiZ buffer. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Resolve buffers in intelSpanRenderStartChad Versace2011-11-221-1/+39
| | | | | | | | | | | | | | | | | | Resolve all buffers that will be mapped by intelSpanRenderStart. This comprises resolving the depth buffer of each enabled texture and of the read and draw buffers. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * intel: Refactor intelSpanRenderStartChad Versace2011-11-221-16/+25
| | | | | | | | | | | | | | | | | | Factor the mapping loops from intelSpanRenderStart() into intel_span_map_buffers(). This in preparation for the next commit, which resolves the buffers before mapping. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965: Resolve buffers before drawing [v2]Chad Versace2011-11-221-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | Before emitting primitives in brw_try_draw_prims(), resolve the depth buffer's HiZ buffer and resolve the depth buffer of each enabled depth texture. v2: [anholt] The driver no longer validates drm bo's, so update a comment to reflect that. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965: Prevent recursive calls to FLUSH_VERTICES [v2]Chad Versace2011-11-221-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | To do so, we must resolve all buffers on entering a glBegin/glEnd block. For the detailed explanation, see the Doxygen comments in this patch. v2: - Fix typo: s/enusure/ensure/. - In brwPrepareExecBegin(), do the same resolves as done by brw_predraw_resolve_buffers(). Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
| * i965/gen6: Manipulate state batches for HiZ meta-ops [v4]Chad Versace2011-11-228-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of the state manipulation is handled by the meta-op state setup. However, some batches need manual intervention. v2: Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets ctx->Depth.Test, just read the value from that. v3: Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it immediately before and after executing the HiZ operation in gen6_resolve_slice(). Add the flag to the the dirty bits for the following state packets: gen6_clip_state gen6_depth_stencil_state gen6_sf_state gen6_wm_state v4: - Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c. This is needed for INTEL_DEBUG=state. - Align brw dirty bit for gen6_depth_stencil_state. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 21:21:01 +0000