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* i965: Increase Sandybridge point size clamp.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | 255.875 matches the hardware documentation. Presumably this was a typo. Found by inspection. Not known to fix any issues. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | pixel_w is the final result; wpos_w is used on gen4 to compute it. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Refactor control flow stack handling.Kenneth Graunke2011-02-221-7/+27
| | | | | | | | | We can't safely use fixed size arrays since Gen6+ supports unlimited nesting of control flow. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke2011-02-221-0/+10
| | | | | | | | | | | | | The code that generates MATH instructions attempts to work around the hardware ignoring source modifiers (abs and negate) by emitting moves into temporaries. Unfortunately, this pass coalesced those registers, restoring the original problem. Avoid doing that. Fixes several OpenGL ES2 conformance failures on Sandybridge. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke2011-02-221-3/+7
| | | | | | | | | | Single-operand math already had these workarounds, but POW (the only two operand function) did not. It needs them too - otherwise we can hit assertion failures in brw_eu_emit.c when code is actually generated. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix shaders that write to gl_PointSize on Sandybridge.Kenneth Graunke2011-02-221-0/+2
| | | | | | | | | gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register, as it's part of the header. Without this fix, writing to gl_PointSize would cause the SF to read and use the wrong attributes, leading to all kinds of random looking failure. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Avoid undeclared ffs function warning on mingw.José Fonseca2011-02-221-0/+6
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* gallium: s/PIPE_TRANSFER_CPU_READ/PIPE_TRANSFER_READ/ in comments.José Fonseca2011-02-221-4/+4
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* gallium/docs: Update PIPE_TRANSFER_xx docs. Reformat to use definitions.José Fonseca2011-02-221-13/+29
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* gallium: new transfer flag: DISCARD_WHOLE_RESOURCEKeith Whitwell2011-02-221-3/+18
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* st/mesa: fix crash when using both user and vbo buffers with the same strideMarek Olšák2011-02-201-0/+8
| | | | | | | | | If two buffers had the same stride where one buffer is a user one and the other is a vbo, it was considered to be one interleaved buffer, resulting in incorrect rendering and crashes. This patch makes sure that the interleaved buffer is either user or vbo, not both.
* st/mesa: fix crash when DrawBuffer->_ColorDrawBuffers[0] is NULLMarek Olšák2011-02-201-6/+10
| | | | This fixes the game Tiny and Big.
* i965: Trim the interleaved upload to the minimum number of verticesChris Wilson2011-02-221-1/+5
| | | | | | ... should have no impact on a properly formatted draw operation. Signed-off-by: Chris Wilson <[email protected]>
* i965: Reinstate max-index paranoiaChris Wilson2011-02-221-1/+1
| | | | | | | Don't trust the applications not to reference beyond the end of the vertex buffers. Signed-off-by: Chris Wilson <[email protected]>
* i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson2011-02-221-0/+1
| | | | | | Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b. Signed-off-by: Chris Wilson <[email protected]>
* st/dri: Track drawable context bindingsJakob Bornecrantz2011-02-204-2/+14
| | | | | | | | | | | | | | | | | | | Needs to track this ourself since because we get into a race condition with the dri_util.c code on make current when rendering to the front buffer. This is what happens: Old context is rendering to the front buffer. App calls MakeCurrent with a new context. dri_util.c sets drawable->driContextPriv to the new context and then calls the driver make current. st/dri make current flushes the old context, which calls back into st/dri via the flush frontbuffer hook. st/dri calls dri loader flush frontbuffer, which calls invalidate buffer on the drawable into st/dri. This is where things gets wrong. st/dri grabs the context from the dri drawable (which now points to the new context) and calls invalidate framebuffer to the new context which has not yet set the new drawable as its framebuffers since we have not called make current yet, it asserts.
* i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt2011-02-211-1/+1
| | | | Fixes regression in scissor-stencil-clear and 5 other tests.
* Revert "mesa: convert macros to inline functions"Brian Paul2011-02-211-22/+22
| | | | | | This reverts commit e9ff76aa81d9bd973d46b7e46f1e4ece2112a5b7. Need to use macros so __FUNCTION__ reports the caller.
* st/mesa: need to translate clear color according to surface's base formatBrian Paul2011-02-214-47/+75
| | | | | | | | | | | When clearing a GL_LUMINANCE_ALPHA buffer, for example, we need to convert the clear color (R,G,B,A) to (R,R,R,A). We were doing this for texture border colors but not renderbuffers. Move the translation function to st_format.c and share it. This fixes the piglit fbo-clear-formats test. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* st/mesa: fix the default case in st_format_datatype()Brian Paul2011-02-211-5/+2
| | | | | | Part of the fix for piglit fbo-clear-formats NOTE: This is a candidate for the 7.9 and 7.10 branches.
* i915g: add some throttlingDaniel Vetter2011-02-211-0/+9
| | | | | | Intel classic drivers switched to this, too, so it must be good. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: s/bool/boolean/ style-fixup in winsysDaniel Vetter2011-02-213-3/+4
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: Fix warningJakob Bornecrantz2011-02-211-1/+0
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* i915g: Add option to lie about capsJakob Bornecrantz2011-02-213-1/+9
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* i915g: Move debug fields to screenJakob Bornecrantz2011-02-214-4/+7
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* i915g: Use debug get once optionsJakob Bornecrantz2011-02-212-3/+9
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* i915g: Rework texture tiling a bitJakob Bornecrantz2011-02-211-14/+8
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* i915g: Anisotropic filtering worksJakob Bornecrantz2011-02-211-1/+1
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* i915g: TODO about point spritesJakob Bornecrantz2011-02-211-0/+3
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* i915g: TODO about untested code hidden behind capsJakob Bornecrantz2011-02-212-2/+9
| | | | | Should be fairly easy to test and fix since you can look at the code in the classic driver.
* i915g: Reorg capsJakob Bornecrantz2011-02-211-28/+42
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* st/mesa: fix incorrect texture size allocation in st_finalize_texture()Brian Paul2011-02-211-3/+18
| | | | | | | | If finalizing a non-POW mipmapped texture with an odd-sized base texture image we were allocating the wrong size of gallium texture (off by one). Need to be more careful about computing the base texture image size. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=34463
* st/mesa: refactor guess_and_alloc_texture() codeBrian Paul2011-02-211-35/+60
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* st/mesa: fix mipmap generation for non-POW texturesBrian Paul2011-02-211-7/+7
| | | | This is part of the fix for https://bugs.freedesktop.org/show_bug.cgi?id=34463
* mesa: convert macros to inline functionsBrian Paul2011-02-211-22/+22
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* vbo: more commentsBrian Paul2011-02-211-0/+5
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* vbo: make vbo_exec_FlushVertices_internal() staticBrian Paul2011-02-212-22/+20
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* vbo: remove old debug code, add commentsBrian Paul2011-02-211-4/+8
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* vbo: rename, document function paramsBrian Paul2011-02-211-5/+5
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* vbo: commentsBrian Paul2011-02-211-0/+8
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* vbo: replace assert(0) with proper assertionsBrian Paul2011-02-211-5/+2
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* vbo: rename some vars, add new comments, fix formatting, etc.Brian Paul2011-02-212-58/+77
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* vbo: use ctx instead of exec->ctxBrian Paul2011-02-211-3/+3
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* radeon: add default switch case to silence unhandled enum warningBrian Paul2011-02-211-0/+2
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* Use C-style system headers in C++ code to avoid issues with std:: namespaceIan Romanick2011-02-2125-58/+8
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* intel: Fix insufficient integer width for upload buffer offsetChris Wilson2011-02-211-2/+2
| | | | | | | | I was being overly miserly and gave the offset of the buffer into the bo insufficient bits, distracted by the adjacency of the buffer[4096]. Ref: https://bugs.freedesktop.org/show_bug.cgi?id=34541 Signed-off-by: Chris Wilson <[email protected]>
* svga: Remove some remaining fake S3TC rendering support.José Fonseca2011-02-211-4/+0
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* i965: Remove spurious duplicate ADVANCE_BATCHChris Wilson2011-02-211-1/+0
| | | | | | ... a leftover from a bad merge. Signed-off-by: Chris Wilson <[email protected]>
* i915: Emit a single relocation per vboChris Wilson2011-02-215-17/+45
| | | | | | | | | Reducing the number of relocations has lots of nice knock-on effects, not least including reducing batch buffer size, auxilliary array sizes (vmalloced and copied into the kernel), processing of uncached relocations etc. Signed-off-by: Chris Wilson <[email protected]>
* i915: Suppress emission of redundant stencil updatesChris Wilson2011-02-211-45/+55
| | | | Signed-off-by: Chris Wilson <[email protected]>
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