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* r600g: add evergreen+ big endian supportAlex Deucher2011-04-194-6/+74
| | | | | | Based on Cédric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add big endian support for r6xx/r7xxCédric Cano2011-04-198-14/+151
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600c: add evergreen big endian supportAlex Deucher2011-04-195-9/+286
| | | | | | Based on Cedric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600c: add big endian support for r6xx/r7xxCédric Cano2011-04-1911-50/+508
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Makefile: add missing Scons filesBrian Paul2011-04-191-0/+15
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* Makefile: add missing .cpp, .ll, .yy filesThierry Vignaud2011-04-191-0/+3
| | | | Signed-off-by: Brian Paul <[email protected]>
* r600g: add cb support for snorm formats.Dave Airlie2011-04-192-9/+13
| | | | | | Check for signed type and enable SNORM. Signed-off-by: Dave Airlie <[email protected]>
* configure.ac: rename --enable-gallium-radeon to --enable-gallium-r300Marek Olšák2011-04-191-9/+8
| | | | Also fix up the help string for both r300 and r600.
* r200: enable some extensionsMarek Olšák2011-04-191-2/+10
| | | | | | | | Such as: - GL_ARB_half_float_pixel - GL_ARB_vertex_array_object - GL_APPLE_vertex_array_object - GL_EXT_gpu_program_parameters
* r600g: fix warnings with piglit texture-rg test.Dave Airlie2011-04-192-0/+6
| | | | | | Fill in the swaps for the formats to fix warnings. Signed-off-by: Dave Airlie <[email protected]>
* r600g: make loop const always flushDave Airlie2011-04-192-2/+2
| | | | | | | | this needs revisiting, we really don't want to be flushing all 32 of these, but currently we don't flush any of them, and it seems to have caused a regression as reported on irc with doom3 on evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r300/compiler: Fix dataflow analysis bug with ELSE blocksTom Stellard2011-04-181-0/+7
| | | | | | | Writes within ELSE blocks were being ignored which prevented us from discovering all possible writers for some register values. Fixes piglit glsl-fs-raytrace-bug27060
* glsl: fix conversions from uint to bool and from float/bool to uintBryan Cain2011-04-181-3/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ian Romanick <[email protected]>
* r600g: add dirty tracking to context reg.Dave Airlie2011-04-191-7/+12
| | | | | | just makes the code more consistent. Signed-off-by: Dave Airlie <[email protected]>
* r600g: deinline some large functions.Dave Airlie2011-04-192-76/+83
| | | | | | really at these sort of sizes these are pointless inlines. Signed-off-by: Dave Airlie <[email protected]>
* r600g: consolidate r600/evergreen code for resource emission.Dave Airlie2011-04-193-41/+8
| | | | | | These really didn't have much difference, and totally not inline material. Signed-off-by: Dave Airlie <[email protected]>
* r600g: don't flush caches if we already did so, even for a subset of the flagsBas Nieuwenhuizen2011-04-191-2/+2
| | | | | | | Merging the flushes that are left doesn't seem to give a significant performance improvement Signed-off-by: Dave Airlie <[email protected]>
* r600g: attempt to avoid emitting resources that are the sameDave Airlie2011-04-191-18/+49
| | | | | | This just avoids reemitting resources that haven't changed. Signed-off-by: Dave Airlie <[email protected]>
* r600g: modify block to only emit the first few dirty registers. (v2)Dave Airlie2011-04-194-12/+39
| | | | | | | | | | | This gets me from 2200 to 1978 dwords for a gears frame. This is due to us having some 32-dwords blocks in the SPI, that we only modify the first dwords off. v2: fix dirty reg count from Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* r600g: track dirty registers better. (v2)Dave Airlie2011-04-194-121/+171
| | | | | | | | | | | | | | | | | | | | | | | | | This is a first step to decreasing the CPU usage, by decreasing how much stuff we pass to the GPU and hence to the kernel CS checker. This adds a check to see if the values we need to write are actually dirty, and avoids writing if they are. However certain register need to always be written so we add a new flag to say which ones should be always written if used. (Note this could probably be done cleaner with a larger refactoring, since I think the CONST_BUFFER_SIZE_PS/VS and CONST_CACHE_PS/VS might be better off as a special state). It also moves the need_bo to be a flags on the register now. With this, a frame of gears goes from emitting 3k dwords to emitting 2k dwords, and I'm sure it could get a lot smaller. v2: fix some evergreen dirty bits. Original patch from: Bas Nieuwenhuizen, I NIHed nearly the same thing before seeing his patch on the list, oops. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* glsl: 80-column wrapping and whitespace fixesIan Romanick2011-04-181-1/+5
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* i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.Kenneth Graunke2011-04-183-46/+37
| | | | | | | | | | Most of the newer portions of the code use OUT_BATCH style. I prefer this style because it offers a clear distinction between a) hardware messages/structures with a mandatory format, and b) data structures for our own internal use that we can format however we want. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Allocate the whole URB to the VS and fix calculations for Gen6.Kenneth Graunke2011-04-183-19/+25
| | | | | | | | | | | | | | | | | Since we never enable the GS on Sandybridge, there's no need to allocate it any URB space. Furthermore, the previous calculation was incorrect: it neglected to multiply by nr_vs_entries, instead comparing whether twice the size of a single VS URB entry was bigger than the entire URB space. It also neglected to take into account that vs_size is in units of 128 byte blocks, while urb_size is in bytes. Despite the above problems, the calculations resulted in an acceptable programming of the URB in most cases, at least on GT2. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Emit a warning when the left-hand operand of a comma has no effectIan Romanick2011-04-181-1/+35
| | | | | | | | | | | | | | | | | The expression x = y, 5, 3; will generate 0:7(9): warning: left-hand operand of comma expression has no effect The warning is only emitted for the left-hand operands, becuase the right-most operand is the result of the expression. This could be used in an assignment, etc. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix void pointer arithmetic warningsBrian Paul2011-04-181-21/+18
| | | | And fix a couple logic errors in the put_*_generic() functions.
* mesa: fix wrong parameter type in set_sampler_max_lod()Brian Paul2011-04-181-1/+1
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* nvfx: comment-out unused varBrian Paul2011-04-181-1/+1
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* intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().Eric Anholt2011-04-181-0/+2
| | | | | | Fixes warnings in fbo-storage-formats. Reviewed-by: Brian Paul <[email protected]>
* Revert "intel: Add spans code for the ARB_texture_rg support."Eric Anholt2011-04-181-122/+0
| | | | | | | | | This reverts what remains of commit 28bab24e1698843e27d27204a1117066e7ffeabb. It was garbage, trying to use a MESA_FORMAT enum as a preprocessor token, and I don't know how I thought it was even tested. Reviewed-by: Brian Paul <[email protected]>
* intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.Eric Anholt2011-04-181-25/+4
| | | | | | | Fixes: ARB_texture_rg/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* swrast: Don't try to adjust_colors for <8bpc when handling R16, RG1616.Eric Anholt2011-04-181-3/+3
| | | | | | | | | The GL_RED and GL_RG were tricking this code into executing, but it's totally unprepared for a 16-bit channel and just rescaled the values down to 0. We don't have anything with <8bit channels alongside >8bit channels, so disabling it should be safe. Reviewed-by: Brian Paul <[email protected]>
* mesa: Add renderbuffer accessors for R8/RG88/R16/RG1616.Eric Anholt2011-04-181-0/+310
| | | | | | | This will replace the current (broken by trying to use an enum in the preprocessor) spantmp2.h support I wrote for the intel driver. Reviewed-by: Brian Paul <[email protected]>
* mesa: Use _mesa_get_format_bytes to refactor out the RB get_row_*Eric Anholt2011-04-181-60/+10
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Use _mesa_get_format_bytes to refactor out the RB get_pointer_*Eric Anholt2011-04-181-66/+11
| | | | Reviewed-by: Brian Paul <[email protected]>
* intel: Use Mesa core's renderbuffer accessors for depth.Eric Anholt2011-04-182-33/+17
| | | | | | | | | | | Since we're using GTT mappings now (no manual detiling), there's really nothing special to accessing these buffers, other than needing the new RowStride field of gl_renderbuffer to accomodate padding. Reduces the driver size by 2.7kb, and improves glean depthStencil performance 3-10x (!) Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a function to set up the default renderbuffer accessors.Eric Anholt2011-04-182-78/+104
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a gl_renderbuffer.RowStride field like textures have.Eric Anholt2011-04-183-53/+66
| | | | | | | | | This will allow some drivers to reuse the core renderbuffer.c get/put row functions in place of using the spantmp.h macros. Note that unlike textures, we use a signed integer here to allow for handling FBO orientation. Reviewed-by: Brian Paul <[email protected]>
* mesa: Repack single-byte fields in gl_renderbuffer.Eric Anholt2011-04-181-4/+4
| | | | | | Cuts 8 out of 120 bytes in the struct. Reviewed-by: Brian Paul <[email protected]>
* mesa: Remove renderbuffer deletion debug field.Eric Anholt2011-04-182-7/+0
| | | | | | | It has presumably served its purpose by now, and other object deletion doesn't do this. Reviewed-by: Brian Paul <[email protected]>
* swrast: Don't assert against glReadPixels of GL_RED and GL_RG.Eric Anholt2011-04-182-2/+8
| | | | | | | | Everything appears to already be in place for this. Fixes aborts in: ARB_texture_rg/fbo-alphatest-formats-float ARB_texture_rg/fbo-blending-formats-float. Reviewed-by: Brian Paul <[email protected]>
* intel: Use _mesa_base_tex_format for FBO texture attachments.Eric Anholt2011-04-181-1/+1
| | | | | | | | | | | | The _mesa_base_fbo_format variant doesn't handle some texture internalformats, such as "3". Fixes: fbo-blending-formats. fbo-alphatest-formats EXT_texture_sRGB/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* r300g: remove non-existing include path from SConscriptMarek Olšák2011-04-181-1/+0
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* r300g/winsys: rename r300->radeon and do a little cleanupMarek Olšák2011-04-1836-593/+586
| | | | | Renaming a few files, types, and functions. Also make the winsys independent of r300g.
* Fix mesa tarball creation againThierry Vignaud2011-04-181-1/+0
| | | | Signed-off-by: Marek Olšák <[email protected]>
* r600g: disable ARB_draw_instancedMarek Olšák2011-04-181-1/+3
| | | | | | | The very presence of this extension breaks things. This should bring us closer to being able to run Unigine Heaven. The extension will be re-enabled once gl_InstanceID is implemented.
* r300g: disable ARB_draw_instanced on SWTCL chipsets.Marek Olšák2011-04-181-1/+1
| | | | This fixes Unigine Heaven.
* i965: Quit spamming gen6 DP read/write send instructions with gen5 bits.Eric Anholt2011-04-171-6/+0
| | | | | | This was copy-and-paste from originally trying to get DP read/write working reliably, and notably for other common messages (URB, sampler) we weren't doing this.
* i965/fs: Add gen6 register spilling support.Eric Anholt2011-04-175-31/+58
| | | | | | | | | | | Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
* mesa: Fix _mesa_unpack_dudv_span_byte assertion.Eric Anholt2011-04-171-1/+2
| | | | | | | It was accepting only GL_DUDV_ATI and not the specific sized format GL_DU8DV8_ATI. Fixes assertion failure at startup in Shadowgrounds. Reviewed-by: Brian Paul <[email protected]>
* glcpp: Fix attempts to expand recursive macros infinitely (bug #32835).Carl Worth2011-04-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 095-recursive-define test case was triggering infinite recursion with the following test case: #define A(a, b) B(a, b) #define C A(0, C) C Here's what was happening: 1. "C" was pushed onto the active list to expand the C node 2. While expanding the "0" argument, the active list would be emptied by the code at the end of _glcpp_parser_expand_token_list 3. When expanding the "C" argument, the active list was now empty, so lather, rinse, repeat. We fix this by adjusting the final popping at the end of _glcpp_parser_expand_token_list to never pop more nodes then this particular invocation had pushed itself. This is as simple as saving the original state of the active list, and then interrupting the popping when we reach this same state. With this fix, all of the glcpp-test tests now pass. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32835 Signed-off-by: Carl Worth <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
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