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* intel: Add offset field to miptreeKristian Høgsberg2012-07-116-8/+18
| | | | | | | | This lets us specify an offset into the bo where the miptree starts, which will let us set up a texture for a single plane in a planar buffer. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Add support for new __DRIimage formatsKristian Høgsberg2012-07-111-0/+15
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* __DRIimage: version 5, add new formats and createSubImageKristian Høgsberg2012-07-111-0/+27
| | | | | | | | | | | | | The additions in version 5 enables creating EGLImages for different planes of a YUV buffer. createImageFromName is still used to create the containing __DRIimage, and createSubImage can then be used no that __DRIimage to create __DRIimages that correspond to the y, u, and v planes (__DRI_IMAGE_FORMAT_R8) or the uv planes (__DRI_IMAGE_FORMAT_RG88) for formats such as NV12 where the u and v components are interleaved. Packed formats such as YUYV etc doesn't require any special treatment, we just sample those as a regular ARGB texture. Signed-off-by: Kristian Høgsberg <[email protected]>
* r600g/compute: Disable growing the memory poolTom Stellard2012-07-114-23/+38
| | | | | | | | | | | | | | | | | | | | | | | The code for growing the memory pool (which is used for storing all of the global buffers) wasn't working. There seem to be two separate issues with the memory pool code. The first was the way it was growing the pool. When the memory pool needed more space, it would: 1. Copy the data from the memory pool's backing texture to system memory. 2. Delete the memory pool's texture 3. Create a bigger backing texture for the memory pool. 4. Copy the data from system memory into the bigger texture. The copy operations didn't seem to be working, and I suspect that since they were using fragment shaders to do the copy, that there might have been a problem with the mixing of compute and 3D state. The other issue is that the size of 1D textures is limited, and I was having trouble getting 2D textures to work. I think these problems will be easier to solve once more code is shared between 3D and compute, which is why I decided to disable it for now rather than continue searching for a fix.
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-117-50/+46
| | | | | | | The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
* radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.Tom Stellard2012-07-111-7/+2
| | | | The IMM bit is already being set in SICodeEmitter.
* r600g/compute: Add more debugging outputTom Stellard2012-07-112-1/+42
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* i965: Revert the VBOs-in-system-memory hack.Eric Anholt2012-07-111-8/+5
| | | | | | | | It didn't change performance on Lightsmark or Nexuiz, which both used DYNAMIC_DRAW buffers, but it was killing performance (40% CPU wasted pwriting buffers) on a closed-source app we're looking at. Reviewed-by: Kenneth Graunke <[email protected]>
* Add emacs setup for the docs/devinfo.html comment wrapping recommendation.Eric Anholt2012-07-111-0/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* glx/dri2: Add support for GLX_ARB_create_context_robustnessIan Romanick2012-07-117-6/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the infrastructure required for this extension. There is no xserver support and no driver support yet. Drivers can enable this be advertising DRI2 version 4 and accepting the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag and the __DRI_CTX_ATTRIB_RESET_STRATEGY attribute in create context. Some additional Mesa infrastructure is needed before drivers can do this. The GL_ARB_robustness spec, which all Mesa drivers already advertise, requires: "If the behavior is LOSE_CONTEXT_ON_RESET_ARB, a graphics reset will result in the loss of all context state, requiring the recreation of all associated objects." It is necessary to land this infrastructure now so that the related infrastructure can land in the xserver. The xserver has very long release schedules, and the remaining Mesa parts should land long, long before the next xserver merge window opens. v2: Expose robustness as a DRI2 extension rather than bumping __DRI_DRI2_VERSION. v3: Add a comment explaining why dri2->base.version >= 3 is also required for GLX_ARB_create_context_robustness. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* dri2: Hard-code the DRI2 versionIan Romanick2012-07-111-1/+1
| | | | | | | | This allows revising the dri_interface.h separately from adding driver support. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glapi: Apply Xorg indent rules to all files generated for the xserverIan Romanick2012-07-111-15/+39
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: Update GL3.txt.Kenneth Graunke2012-07-101-2/+2
| | | | | | | | | | | | | We neglected to list the deprecation model/forward compatible context support. inverse() has been done for a while. None of us know what "highp change" means; GLSL 1.30 already added the ability to recognize precision keywords, and it doesn't look like 1.40 has any new requirements there (precision keywords still have no meaning). Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: Remove unneeded extern qualifiersChad Versace2012-07-101-2/+2
| | | | | | | Remove 'extern' from the functions declared in texcompress_etc.h. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* r600g: improve flushed depth texture handling v2Vadim Girlin2012-07-116-61/+83
| | | | | | | | | | | Use r600_resource_texture::flished_depth_texture for GPU access, and allocate it in the VRAM. For transfers we'll allocate texture in the GTT and store it in the r600_transfer::staging. Improves performance when flushed depth texture is frequently used by the GPU, e.g. in Lightsmark (~30%) Signed-off-by: Vadim Girlin <[email protected]>
* i965: Add hardware context support.Kenneth Graunke2012-07-105-7/+22
| | | | | | | | | | | With fixes and updates from Ben Widawsky and comments from Paul Berry. v2: Use drm_intel_gem_context_destroy to destroy hardware context; remove useless initialization of hw_ctx, both suggested by Eric. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Paul Berry <[email protected]>
* mesa/test: Update name of GL_TIME_ELAPSEDIan Romanick2012-07-101-1/+1
| | | | | | | | 4952caa caused the _EXT to fall off the name of this enum. This is fine. Update the unit test to expect the new value. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51956
* docs/relnotes-8.0.4: fix html markupAndreas Boll2012-07-101-44/+41
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* gallium/docs: document interface changes for timestamp queryMarek Olšák2012-07-101-0/+10
| | | | the query type is already documented
* identity: implement get_timestampMarek Olšák2012-07-101-0/+10
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* noop: implement get_timestampMarek Olšák2012-07-101-0/+6
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* trace: implement get_timestampMarek Olšák2012-07-101-0/+19
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* galahad: implement get_timestampMarek Olšák2012-07-101-0/+10
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* docs: update relnotes-8.1 and GL3 statusMarek Olšák2012-07-102-1/+4
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* softpipe: implement get_timestamp and expose ARB_timer_queryMarek Olšák2012-07-101-1/+10
| | | | PIPE_QUERY_TIMESTAMP is already implemented and working.
* st/mesa: implement ARB_timer_queryMarek Olšák2012-07-102-0/+19
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* gallium: add QUERY_TIMESTAMP cap and get_timestamp screen functionMarek Olšák2012-07-1011-1/+18
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* mesa: implement glGet(GL_TIMESTAMP) v2Marek Olšák2012-07-102-1/+20
| | | | | | This is adds a new driver function to retrieve the timestamp. Reviewed-by: Eric Anholt <[email protected]>
* mesa: add ARB_timer_query to the extension listMarek Olšák2012-07-101-0/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: add QueryCounter display list supportMarek Olšák2012-07-101-0/+24
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: implement TIMESTAMP query and glQueryCounterMarek Olšák2012-07-101-6/+72
| | | | Reviewed-by: Brian Paul <[email protected]>
* glapi: add ARB_timer_queryMarek Olšák2012-07-101-1/+21
| | | | Reviewed-by: Brian Paul <[email protected]>
* docs: Add 8.0.4 release notesIan Romanick2012-07-103-0/+213
| | | | | | Also add news story. Extra, extra! Read all about it! Signed-off-by: Ian Romanick <[email protected]>
* glsl: Add parsing for GLSL uniform blocks.Eric Anholt2012-07-094-2/+164
| | | | | | | | This doesn't do anything with the uniform block declarations yet, so usage of those uniforms finds them to be undeclared. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Don't hide the type of struct_declaration_list.Eric Anholt2012-07-093-5/+9
| | | | | | | | I've been trying to derive from this for UBO support, and the slightly obfuscated types were putting me over the edge. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glcpp: Add built-in #define for GL_ARB_uniform_buffer_object.Kenneth Graunke2012-07-091-0/+3
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Parser handles "#extension GL_ARB_uniform_buffer_object"Vincent Lejeune2012-07-092-0/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Reduce a bit of extra code in the merging of layout qualifiers.Eric Anholt2012-07-091-7/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Take advantage of the layout qualifier flags union to clean up parsing.Eric Anholt2012-07-091-21/+7
| | | | | | | | | The got_one variable was set iff one of the bits in flags.i was set. v2: Fix incorrect dropping of the ARB_conservative_depth warning. Reviewed-by: Kenneth Graunke <[email protected]> (v1) Reviewed-by: Ian Romanick <[email protected]>
* r600g: Don't create a texture for the memory_pool during screen initTom Stellard2012-07-092-8/+24
| | | | | | | This fixes a segfault in r600_screen_create() introduced by eb065f5d9d1159af3a88a64a7606c9b6d67dc3 Reported by tilman on irc.
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-0925-360/+361
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* r600g: Update number of gprs when adding a vertex instructionTom Stellard2012-07-091-0/+4
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* r600g/compute: Use evergreen_cb() for binding RATsTom Stellard2012-07-095-70/+48
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* r600g: Add support for RATs in evergreen_cb()Tom Stellard2012-07-091-3/+11
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* r600g: Use a texture as the underlying resource for compute_memory_poolTom Stellard2012-07-092-18/+37
| | | | This the first step towards being able to use evergreen_cb to bind RATs.
* r600g: Add is_rat flag to r600_resource_textureTom Stellard2012-07-091-0/+1
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* r600g: Add r600_context_pipe_state_emit()Tom Stellard2012-07-092-6/+71
| | | | | | | | This function is used when dispatching compute shader in order to avoid mixing compute and 3D registers in the context's dirty list. This allows the compute code to resuse 3D functions like evergreen_cb, which return a struct r600_pipe_state and still have control over when and how the register writes are emitted.
* r600g: Add pkt_flag parameter to r600_context_block_emit_dirty()Tom Stellard2012-07-093-3/+15
| | | | | | | This allows the shader type bit to be set in the pm4 header when emitting registers for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Move LOOP_CONST initialization to start_compute_cs atomTom Stellard2012-07-091-14/+16
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* r600g: Add start_compute_cs atom to struct r600_contextTom Stellard2012-07-094-94/+96
| | | | | | | | | The start_compute_cs atom initializes some config and context registers to the values needed for running compute shaders. When a compute shader is dispatched, this atom is emitted after the start_cs_cmd atom, which initializes registers that are common to both 3D and compute. Reviewed-by: Marek Olšák <[email protected]>
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