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* i915g: Fix closure of full batch buffersChris Wilson2010-12-022-72/+30
| | | | | | | | Signed-off-by: Chris Wilson <[email protected]> [danvet: incorporate comments by Dr_Jakob] Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: track TODO itemsDaniel Vetter2010-12-021-0/+29
| | | | | | | | Just as a reminder for all things currently broken with i915g. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: assert(depth_surface->offset == 0)Daniel Vetter2010-12-021-1/+2
| | | | | | | | Shouldn't happen and not supported, anyway. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: enable x-tiling for render targetsDaniel Vetter2010-12-021-4/+0
| | | | | | Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: switch rendering to mipmapped textures to (x,y) offsetsDaniel Vetter2010-12-023-9/+29
| | | | | | | | | | | | | Byte offsets simply don't work with tiled render targets when using tiling bits. Luckily we can cox the hw into doing the right thing with the DRAWING_RECT command by disabling the drawing rect offset for the depth buffer. Minor fixes by Jakob Bornecrantz. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: enable X-tiling for texturesDaniel Vetter2010-12-023-0/+27
| | | | | | | | | Tiling is rather fragile in general and results in pure blackness when unlucky. Hence add a new option to disable tiling. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: don't pot-align stride for tiled buffersDaniel Vetter2010-12-021-2/+3
| | | | | | | | | libdrm will do this for us, if it's required (i.e. if tiling is possible). Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: postpone mipmap/face offset calculationDaniel Vetter2010-12-023-27/+43
| | | | | | | | | | | | | | | | | | | | libdrm-intel can refuse to tile buffers for various reasons. For potentially tiled buffers the stride is therefore only known after the iws->buffer_create_tiled call. Unconditionally rounding up to whatever tiling requires wastes space, so rework the code to not use tex->stride in the layout code. Luckily only the mimap/face offset calculation uses it which can easily be solved by storing an (x, y) coordinate pair. Furthermore this will be usefull later for properly supporting rendering into the different levels of tiled mipmap textures. v2: switch to nblocks(x|y): More in line with gallium and better suited for rendering into mipmap textures. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: implement unfenced relocs for textures using tiling bitsDaniel Vetter2010-12-023-5/+20
| | | | | | Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: implement unfenced color&depth buffer using tiling bitsDaniel Vetter2010-12-022-8/+22
| | | | | | | | v2: Clarify tiling bit calculation as suggested by Chris Wilson. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: return tiling in iws->buffer_from_handleDaniel Vetter2010-12-023-3/+9
| | | | | | | | | | This is needed to properly implement tiling flags. And the gem implemention fo buffer_from_handle already calls get_tiling, so it's for free. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: prepare winsys/batchbuffer for execbuf2Daniel Vetter2010-12-028-27/+38
| | | | | | | | Wire up a fenced parameter, switch all relocations to _FENCED Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: switch to tiled allocations, kill set_fenceDaniel Vetter2010-12-024-60/+2
| | | | | | | | | This way relaxed fencing is handled by libdrm. And buffers _can't_ ever change their tiling. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: add winsys function to create tiled buffersDaniel Vetter2010-12-024-14/+102
| | | | | | | | | | | | | | Different kernels have different restrictions for tiled buffers. Hence use the libdrm abstraction to calculate the necessary stride and height alignment requirements. Not yet used. v2: Incorporate review comments from Jakob Bornecrantz Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: drop alignment parameter from iws->buffer_createDaniel Vetter2010-12-026-21/+7
| | | | | | | | | | | | It's unnecessary. The kernel gem ignores it totally and we can't run on the old userspace fake bo manager due to lack of dri2. Also drop the redundant name string from the sw winsys as suggested by Jakob Bornecrantz Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* glsl: Mark the array access for whole-array comparisons.Eric Anholt2010-12-011-0/+14
| | | | | | By not doing so, the uniform contents of glsl-uniform-non-uniform-array-compare.shader_test was getting thrown out since nobody was recorded as dereferencing the array.
* i965: Add support for loops in the VS.Eric Anholt2010-12-011-25/+33
| | | | This follows the changes done for the FS alongside the EU emit code.
* i965: Enable IF statements in the VS.Eric Anholt2010-12-011-3/+0
| | | | | While the actual IF instructions were fixed by Zhenyu, we were still flattening them to conditional moves.
* i965: Add support for gen6 CONTINUE instruction emit.Eric Anholt2010-12-013-4/+28
| | | | At this point, piglit tests for fragment shader loops are working.
* i965: Add support for gen6 BREAK ISA emit.Eric Anholt2010-12-014-10/+112
| | | | | There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
* i965: Add support for gen6 DO/WHILE ISA emit.Eric Anholt2010-12-012-30/+74
| | | | | There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
* i965: Dump the WHILE jump distance on gen6.Eric Anholt2010-12-011-1/+2
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* r300g: disable ARB_texture_swizzle if S3TC is enabled on r3xx-onlyMarek Olšák2010-12-011-1/+2
| | | | | | r3xx cannot swizzle compressed textures. r4xx+ is unaffected. NOTE: This is a candidate for the 7.9 branch.
* r300g: fix texture swizzling with compressed textures on r400-r500Marek Olšák2010-12-017-13/+28
| | | | | | This fixes all S3TC piglit/texwrap tests. NOTE: This is a candidate for the 7.9 branch.
* i915: Correctly generate unconditional KIL instructionsIan Romanick2010-12-011-1/+5
| | | | | | Fixes piglit test glsl-fs-discard-03. NOTE: This is a candidate for the 7.9 branch.
* i915: Request that POW instructions be loweredIan Romanick2010-12-011-0/+1
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* glsl: Lower ir_binop_pow to a sequence of EXP2 and LOG2Ian Romanick2010-12-014-4/+33
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* glsl: Use M_LOG2E constant instead of calling log2Ian Romanick2010-12-012-3/+7
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* glsl: Add comments to lower_jumps (from the commit message).Kenneth Graunke2010-12-011-0/+31
| | | | | This is essentially Luca's commit message, but placed at the top of the file.
* glsl: Remove "discard" support from lower_jumps.Kenneth Graunke2010-12-011-11/+2
| | | | | | | | | | | | The new lower_discard and opt_discard_simplification passes should handle all the necessary transformations, so lower_jumps doesn't need to support it. Also, lower_jumps incorrectly handled conditional discards - it would unconditionally truncate all code after the discard. Rather than fixing the bug, simply remove the code. NOTE: This is a candidate for the 7.9 branch.
* glsl: Add a lowering pass to move discards out of if-statements.Kenneth Graunke2010-12-015-1/+204
| | | | | | | This should allow lower_if_to_cond_assign to work in the presence of discards, fixing bug #31690 and likely #31983. NOTE: This is a candidate for the 7.9 branch.
* glsl: Add an optimization pass to simplify discards.Kenneth Graunke2010-12-015-0/+184
| | | | NOTE: This is a candidate for the 7.9 branch.
* ir_to_mesa: Add support for conditional discards.Marek Olšák2010-12-011-2/+7
| | | | | | | NOTE: This is a candidate for the 7.9 branch. Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* r600c: fix some opcodes on evergreenAlex Deucher2010-12-011-8/+56
| | | | | | | | | | There were a few places where we were using the wrong opcodes on evergreen. arl still needs to be fixed on evergreen; see r600g for reference. NOTE: This is a candidate for the 7.9 branch. Signed-off-by: Alex Deucher <[email protected]>
* r300/compiler: implement and lower OPCODE_CLAMPMarek Olšák2010-12-014-1/+29
| | | | Needed for st/vega.
* vega: Remove extraneous ;José Fonseca2010-12-011-1/+1
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* scons: Move MSVS_VERSION option to common module.José Fonseca2010-12-012-1/+1
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* svga: Silence debug printf.José Fonseca2010-12-011-1/+0
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* st/vega: Avoid unnecessary constant bufer upload.Chia-I Wu2010-12-011-30/+48
| | | | Remember the last uploaded data and avoid re-uploading.
* st/vega: Initialize pipe states with renderer.Chia-I Wu2010-12-013-26/+28
| | | | | Initialize vertex elements, rasterizer, stencil ref, and vertex shader with renderer_create. Remove RASTERIZER_DIRTY and VS_DIRTY flags.
* st/vega: Create drawing surface mask as needed.Chia-I Wu2010-12-013-35/+38
| | | | | | | As the blend texture, a drawing surface mask is used when masking is enabled. It should be created as needed. s/alpha_mask/surface_mask/ to follow OpenVG 1.1 naming.
* st/vega: Delay blend texture creation until needed.Chia-I Wu2010-12-014-57/+32
| | | | | It is used for more advanced blending or mask update. It might not be ever needed for some applications.
* st/vega: Remove st_inlines.h.Chia-I Wu2010-12-015-127/+1
| | | | Per b0427bedde80e3189524651a327235bdfddbc613.
* st/vega: Simplify radial gradient.Chia-I Wu2010-12-011-73/+46
| | | | Eight less instructions with comments.
* st/vega: Fix degenerate paints.Chia-I Wu2010-12-016-9/+80
| | | | | Fix the case that the two points of a linear gradient coincide, or the case that the radius of a radial gradient is equal to or less than 0.
* i965: also using align1 mode for math2 on sandybridgeZhenyu Wang2010-12-011-6/+50
| | | | | Like Eric's workaround patch of commit 490c23ee6be2e8531b5a14d42f808de83d401130. This forces to align1 mode for math2 too.
* st/vega: Fix negated logic in image_draw.Chia-I Wu2010-12-011-4/+4
| | | | A typo from last commit.
* st/vega: Fix paint coordinates transformations.Chia-I Wu2010-12-019-39/+94
| | | | | | | | Depending on whether vgDrawPath(mode), vgDrawImage, or vgDrawGlyph[s] is called, different paint-to-user and user-to-surface matrices should be used to derive the sample points for the paint. This fixes "paint" demo.
* st/vega: Bump version to 1.1.Chia-I Wu2010-12-011-2/+2
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* st/vega: Add color transformation support.Chia-I Wu2010-12-017-50/+123
| | | | | Per OpenVG 1.1. A new shader stage is added. It uses the first two constants of the fragment shader for color transformation parameters.
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