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* gallium: add sparse buffer interface and capabilityNicolai Hähnle2017-04-0519-0/+58
| | | | | | | v2: - explain the resource_commit interface in more detail Reviewed-by: Marek Olšák <[email protected]>
* mesa: implement sparse buffer commitmentNicolai Hähnle2017-04-052-0/+76
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: implement sparse storage buffer allocationNicolai Hähnle2017-04-051-6/+23
| | | | | | | v2: - spec quote and style (Ian) Reviewed-by: Marek Olšák <[email protected]>
* mesa: implement SPARSE_BUFFER_PAGE_SIZE_ARBNicolai Hähnle2017-04-053-0/+7
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Add GL_ARB_sparse_buffer boilerplateNicolai Hähnle2017-04-058-0/+59
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* configure.ac: require libdrm_amdgpu 2.4.77Nicolai Hähnle2017-04-051-1/+1
| | | | | | The sparse buffer implementation requires amdgpu_bo_va_op_raw. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Replace program locks with atomic inc/dec.Matt Turner2017-04-053-15/+3
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv: Advertise larger heap sizesJason Ekstrand2017-04-043-14/+75
| | | | | | | | | | | Instead of just advertising the aperture size, we do something more intelligent. On systems with a full 48-bit PPGTT, we can address 100% of the available system RAM from the GPU. In order to keep clients from burning 100% of your available RAM for graphics resources, we have a nice little heuristic (which has received exactly zero tuning) to keep things under a reasonable level of control. Reviewed-by: Kristian H. Kristensen <[email protected]>
* anv: Add support for 48-bit addressesJason Ekstrand2017-04-045-0/+54
| | | | | | | | | | | | | | | | | | This commit adds support for using the full 48-bit address space on Broadwell and newer hardware. Thanks to certain limitations, not all objects can be placed above the 32-bit boundary. In particular, general and state base address need to live within 32 bits. (See also Wa32bitGeneralStateOffset and Wa32bitInstructionBaseOffset.) In order to handle this, we add a supports_48bit_address field to anv_bo and only set EXEC_OBJECT_SUPPORTS_48B_ADDRESS if that bit is set. We set the bit for all client-allocated memory objects but leave it false for driver-allocated objects. While this is more conservative than needed, all driver allocations should easily fit in the first 32 bits of address space and keeps things simple because we don't have to think about whether or not any given one of our allocation data structures will be used in a 48-bit-unsafe way. Reviewed-by: Kristian H. Kristensen <[email protected]>
* anv: Replace anv_bo::is_winsys_bo with a uint32_t flagsJason Ekstrand2017-04-043-9/+11
| | | | Reviewed-by: Kristian H. Kristensen <[email protected]>
* i965/blorp: Align vertex buffers to 64BJason Ekstrand2017-04-041-1/+13
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* anv/blorp: Align vertex buffers to 64BJason Ekstrand2017-04-041-1/+14
| | | | | | | | | | This fixes issues seen when adding support for full 48-bit addresses. The 48-bit addresses themselves have nothing to do with it other than that it caused the kernel to place buffers slightly differently so they interacted differently with the caches. Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* anv: Query the kernel for reset statusJason Ekstrand2017-04-044-40/+107
| | | | | | | | | | | | When a client causes a GPU hang (or experiences issues due to a hang in another client) we want to let it know as soon as possible. In particular, if it submits work with a fence and calls vkWaitForFences or vkQueueQaitIdle and it returns VK_SUCCESS, then the client should be able to trust the results of that rendering. In order to provide this guarantee, we have to ask the kernel for context status in a few key locations. Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Check for device loss at the end of WaitForFencesJason Ekstrand2017-04-041-5/+14
| | | | | | | It's possible that the device could have been lost while we were waiting. We should let the user know if this has happened. Reviewed-by: Kenneth Graunke <[email protected]>
* anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndexJason Ekstrand2017-04-041-3/+24
| | | | | | | | | | When the shader does not set one of these values, they are supposed to get a default value of 0. We have hardware bits in 3DSTATE_CLIP for this but haven't been setting them. This fixes the intermittent failure of dEQP-VK.geometry.layered.3d.render_to_default_layer. Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* i965/fs: Always provide a default LOD of 0 for TXS and TXLJason Ekstrand2017-04-041-9/+9
| | | | | | | | | | | | | We already provide a default LOD for textureQueryLevels and texture() on non-fragment stages. However, there are more cases where one is needed such as textureSize(gsampler2DMS*) in SPIR-V. Instead of trying to list out all of the cases one at a time, just provide the default for all TXS and TXL operations. This fixes a shader validation error in the new Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391 Reviewed-by: Anuj Phogat <[email protected]> Cc: "13.0 17.0" <[email protected]>
* mesa: Require mipmap completeness for glCopyImageSubData(), sometimes.Kenneth Graunke2017-04-041-2/+23
| | | | | | | | | | This patch makes glCopyImageSubData require mipmap completeness when the texture object's built-in sampler object has a mipmapping MinFilter. Fixes (on i965): dEQP-GLES31.functional.debug.negative_coverage.*.buffer.copy_image_sub_data Reviewed-by: Roland Scheidegger <[email protected]>
* libgl-xlib: Link with libunwind.Vinson Lee2017-04-041-1/+2
| | | | | | | | | | | | | | | | | | Fix linking error. CXXLD libGL.la ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `debug_backtrace_capture': src/gallium/auxiliary/util/u_debug_stack.c:59: undefined reference to `_Ux86_64_getcontext' src/gallium/auxiliary/util/u_debug_stack.c:60: undefined reference to `_ULx86_64_init_local' src/gallium/auxiliary/util/u_debug_stack.c:62: undefined reference to `_ULx86_64_step' src/gallium/auxiliary/util/u_debug_stack.c:71: undefined reference to `_ULx86_64_get_proc_info' src/gallium/auxiliary/util/u_debug_stack.c:73: undefined reference to `_ULx86_64_get_proc_name' src/gallium/auxiliary/util/u_debug_stack.c:65: undefined reference to `_ULx86_64_step' Fixes: 70c272004f72 ("gallium/util: libunwind support") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100562 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* intel/isl: Refactor and clerify gen8 alignment calculationsJason Ekstrand2017-04-041-15/+49
| | | | | | | | Adding the actual table from the docs makes it clearer exactly what the restrictions are. In particular, it becomes clear that compressed textures ignore the alignment parameters in RENDER_SURFACE_STATE. Reviewed-by: Chad Versace <[email protected]>
* drirc: Set glsl_zero_init for Kerbal Space Program.Francisco Jerez2017-04-041-0/+8
| | | | | | | | | | | This fixes the stripes of garbage rendered on the floor of the vehicle assembly building among other rendering issues. The reason for the misrendering seems to be that some of the GLSL shaders used by the application use variables before initializing them, incorrectly assuming that they will be implicitly set to zero by the implementation. Acked-by: Matt Turner <[email protected]>
* intel: tools: add aubinator_error_decode toolLionel Landwerlin2017-04-045-1/+766
| | | | | | | | | | | | | | | | This is pretty much the same tool as what i-g-t has, only with a more fancy decoding of the instructions/registers. It also doesn't support anything before gen4. v2 (from Matt): Drop authors Remove undefined automake variable v3: Fix incorrect offsets for dword > 1 (Jordan) v4: Fix decompression error with large blobs (Jordan) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Matt Turner <[email protected]>
* intel: genxml: add RING_BUFFER_CTL registersLionel Landwerlin2017-04-045-0/+272
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add FAULT_REG registerLionel Landwerlin2017-04-045-0/+206
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add gen7 ERR_INT registerLionel Landwerlin2017-04-042-0/+22
| | | | | | | v2: add register to gen7.5 (Matt) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add ACTHD registersLionel Landwerlin2017-04-042-0/+32
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add GFX_ARB_ERROR_RPT registerLionel Landwerlin2017-04-045-0/+73
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add INSTDONE registersLionel Landwerlin2017-04-045-0/+387
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* targets: export radeon winsys_create functions to silence LLVM warningMarek Olšák2017-04-043-0/+15
| | | | | | | | | | | | It silences the following radeonsi LLVM warning due to a previous commit adding an LLVM workaround: "mesa: for the -simplifycfg-sink-common option: may only occur zero or one times!" Cc: 17.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by; Emil Velikov <[email protected]>
* r600g: check rasterizer primitive states like in radeonsiConstantine Kharlamov2017-04-041-8/+13
| | | | | | | | | | | | Specifically, non-line primitives skipped, and defaulting to reset on each packet. The skip of non-line primitives saves ≈110 resetting of PA_SC_LINE_STIPPLE register per frame in Kane&Lynch2. Signed-off-by: Constantine Kharlamov <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600g: extract a code into a r600_emit_rasterizer_prim_state()Constantine Kharlamov2017-04-043-14/+33
| | | | | | | | | | | Also change gs_output_prim type: unsigned → pipe_prim_type. The idea of the code is mostly taken from radeonsi. The new code operating on prev/curr rast_primitives saves ≈15 reloads of PA_SC_LINE_STIPPLE per frame in Kane&Lynch2 Signed-off-by: Constantine Kharlamov <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600g/radeonsi: use the correct types (taken from pipe_draw_info)Constantine Kharlamov2017-04-043-7/+8
| | | | | | | | | | | Note: si_shader.h has also "type" variable that should be changed to "enum pipe_prim_type", however it triggers a bunch of warnings about unhandled switches, so due not knowing the correct way to handle them, I decided to leave it as is. Signed-off-by: Constantine Kharlamov <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600g: remove duplicate memset by using a pointer, and constify argsConstantine Kharlamov2017-04-041-22/+19
| | | | | | Signed-off-by: Constantine Kharlamov <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* glsl: remove unused fileElie TOURNIER2017-04-041-206/+0
| | | | | | | | | | | udivmod64 appears in src/compiler/glsl/builtin_int64.h and src/compiler/glsl/udivmod.h The second file seems unused. Fix commit 6b03b345eb64e15e577bc8b2cf04b314a4c70537 This change doesn't affect shader-db. Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: access gallivm through ctx in most placesMarek Olšák2017-04-043-87/+79
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ctx->types instead of bld->types etc.Marek Olšák2017-04-042-23/+21
| | | | | | even vec_type is f32. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use i32_0/1 instead of *int_bld.zero/one in most placesMarek Olšák2017-04-042-55/+47
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: decrease the size of pipe_draw_info - 88 -> 80 bytesMarek Olšák2017-04-042-3/+9
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_vertex_element - 16 -> 8 bytesMarek Olšák2017-04-041-8/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_resource - 64 -> 48 bytesMarek Olšák2017-04-048-33/+41
| | | | | | | Some other changes needed here. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_box - 24 -> 16 bytesMarek Olšák2017-04-041-4/+7
| | | | | | | | | | | | Also: pipe_transfer: 48 -> 40 bytes. pipe_blit_info = 176 -> 160 bytes. v2: add a comment at pipe_box Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_sampler_view - 48 -> 32 bytesMarek Olšák2017-04-041-6/+6
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_surface - 48 -> 40 bytesMarek Olšák2017-04-041-5/+4
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_framebuffer_state - 96 -> 80 bytesMarek Olšák2017-04-041-4/+4
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_stream_output_info - 532 -> 268 bytesMarek Olšák2017-04-043-4/+4
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: decrease the size of pipe_rasterizer_state - 36 -> 32 bytesMarek Olšák2017-04-041-1/+7
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-0417-2132/+3298
| | | | | | | | | | | | | | | | | | | | | | | Highlights: - Display needs tiled pitch alignment to be at least 32 pixels - Implement Addr2ComputeDccAddrFromCoord(). - Macro-pixel packed formats don't support Z swizzle modes - Pad pitch and base alignment of PRT + TEX1D to 64KB. - Fix support for multimedia formats - Fix a case "PRT" entries are not selected on SI. - Fix wrong upper bits in equations for 3D resource. - We can't support 2d array slice rotation in gfx8 swizzle pattern - Set base alignment for PRT + non-xor swizzle mode resource to 64KB. - Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture - Add stereo support - Optimize swizzle mode selection - Report pitch and height in pixels for each mip - Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG - Correct tcCompatible flag output for mipmap surface - Other fixes and cleanups Acked-by: Alex Deucher <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: use i32_0 and i32_1 moreMarek Olšák2017-04-041-16/+16
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove most uses of lp_build_const*Marek Olšák2017-04-043-151/+145
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up 'radeon_bld' referencesMarek Olšák2017-04-041-60/+48
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix broken texture filtering on SI-CIK since GFX9 changesMarek Olšák2017-04-041-15/+17
| | | | | | | | Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+. Fixes: 5abf60076ce4 ("radeonsi/gfx9: image descriptor changes in mutable fields") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100531 Reviewed-by: Nicolai Hähnle <[email protected]>
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