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* radv: move RADV_TRACE_FILE functions to radv_debug.cSamuel Pitoiset2017-09-019-23/+80
* radv: silent a compiler warning in radv_emit_framebuffer_state()Samuel Pitoiset2017-09-011-3/+3
* radv: compute correct maximum wave count per SIMDSamuel Pitoiset2017-09-011-1/+12
* st/mesa: only try to create 1x msaa surfaces for "fake" msaa driversBrian Paul2017-08-313-14/+24
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nvc0: write 0 to pipeline_statistics.cs_invocationsKarol Herbst2017-08-311-0/+1
* llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 loadBen Crocker2017-09-011-2/+28
* gallivm: correct channel shift logic on big endianRay Strode2017-09-011-1/+7
* util: only use SCHED_IDLE in pthread_setschedparam() when it's definedRoland Scheidegger2017-09-011-1/+1
* anv/formats: Nicely handle unknown VkFormat enumsJason Ekstrand2017-08-311-5/+14
* vbo: fix offset in minmax cache keyCharmaine Lee2017-08-301-3/+5
* anv: fix build errors on androidTapani Pälli2017-08-311-2/+3
* winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2Christian König2017-08-313-5/+27
* radeonsi: set a per-buffer flag that disables inter-process sharing (v4)Marek Olšák2017-08-314-28/+56
* i965: Use BLORP for buffer object stall avoidance blits instead of BLT.Kenneth Graunke2017-08-301-11/+11
* i965: Always flush caches after blitting to a GL buffer object.Kenneth Graunke2017-08-301-1/+3
* i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().Kenneth Graunke2017-08-301-0/+1
* i965: Add a brw_blorp_copy_buffers() command.Kenneth Graunke2017-08-302-0/+29
* blorp: Make blorp_buffer_copy work on Gen4-6.Kenneth Graunke2017-08-301-9/+10
* blorp: Turn anv_CmdCopyBuffer into a blorp_buffer_copy() helper.Kenneth Graunke2017-08-303-99/+143
* radv: don't assert on empty hash tableGrazvydas Ignotas2017-08-311-0/+3
* svga: include sample count in surface_size() computationBrian Paul2017-08-301-1/+1
* i965: drop unused brw->needs_unlit_centroid_workaroundLionel Landwerlin2017-08-302-11/+0
* i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin2017-08-305-8/+9
* i965: drop unused brw->no_simd8Lionel Landwerlin2017-08-301-1/+0
* i965: drop unused brw->has_plnLionel Landwerlin2017-08-302-2/+0
* i965: drop brw->must_use_separate_stencil in favor of devinfo'sLionel Landwerlin2017-08-304-4/+5
* i965: drop unused brw->has_negative_rhw_bugLionel Landwerlin2017-08-302-2/+0
* i965: drop unused brw->has_compr4Lionel Landwerlin2017-08-302-2/+0
* i965: drop brw->has_llc in favor of devinfo->has_llcLionel Landwerlin2017-08-307-8/+8
* i965: drop brw->is_broxtonLionel Landwerlin2017-08-304-5/+2
* i965: drop brw->is_cherryview in favor of devinfo->is_cherryviewLionel Landwerlin2017-08-303-4/+4
* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-3023-44/+45
* i965: drop brw->is_baytrail in favor of devinfo->is_baytrailLionel Landwerlin2017-08-308-13/+13
* i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin2017-08-308-12/+10
* i965: drop brw->gt in favor of devinfo->gtLionel Landwerlin2017-08-305-8/+5
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-3047-311/+506
* anv: use device->info instead of brw->is_*Lionel Landwerlin2017-08-301-1/+1
* Revert "egl: Allow creation of per surface out fence"Mark Janes2017-08-308-106/+18
* i965: add 2xMSAA 16xMSAA modes to DRI configs.Kevin Rogovin2017-08-301-5/+18
* Revert "i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9."Kenneth Graunke2017-08-301-10/+3
* mesa/st: remove unwanted backup fileEric Engestrom2017-08-301-479/+0
* egl/dri2: only destroy created objectsMichael Olbrich2017-08-301-3/+6
* egl: Allow creation of per surface out fenceZhongmin Wu2017-08-308-18/+106
* winsys/amdgpu: add BO to the global list only when RADEON_ALL_BOS is setSamuel Pitoiset2017-08-304-11/+17
* radeonsi: update dirty_level_mask before dispatchingSamuel Pitoiset2017-08-302-0/+6
* anv: set right datatypes in anv_pipeline_bindingJuan A. Suarez Romero2017-08-303-4/+4
* llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSORBrian Paul2017-08-291-0/+6
* i965: Bump the initial program cache size from 4kB to 16kB.Kenneth Graunke2017-08-291-1/+1
* i965: Issue performance warnings when growing the program cacheKenneth Graunke2017-08-291-0/+3
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