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* radeonsi: use multi-threaded compilation in debug contextsNicolai Hähnle2016-07-081-4/+4
| | | | | | | | We only have to stay single-threaded when debug output must be synchronous. This yields better parallelism in shader-db runs for me. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: set debug callback async flagNicolai Hähnle2016-07-084-5/+8
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add async flag to pipe_debug_callbackNicolai Hähnle2016-07-083-2/+14
| | | | | | | v2: fix typo db -> cb Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: catch a potential state tracker error with non-MSAA FBsNicolai Hähnle2016-07-081-0/+6
| | | | | | At least st/mesa ensures this, so I'd rather not handle deviations in radeonsi. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: explicitly choose center locations for 1xAA on PolarisNicolai Hähnle2016-07-085-18/+48
| | | | | | | | | | | | | Unlike SC, the small primitive filter does not automatically use center locations in 1xAA mode, so this is needed to avoid artifacts caused by the small primitive filter discarding triangles that it shouldn't. As a side effect of how the effective number of samples is now calculated, this patch also avoids submitting the sample locations for line/poly smoothing when they're not really needed. Cc: 12.0 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: call cayman_emit_msaa_sample_locs only when neededNicolai Hähnle2016-07-081-1/+2
| | | | | | In the case of nr_samples <= 1, that function is (currently) a no-op anyway. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Mark R*32F formats as filterable when an extension is present.Kenneth Graunke2016-07-083-3/+19
| | | | | | | | | | | GL_OES_texture_float_linear marks R32F, RG32F, RGB32F, and RGBA32F as texture filterable. Fixes glGenerateMipmap GL errors when visiting a WebGL demo in Chromium: http://www.iamnop.com/particles Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965/blorp: fix indentation levelEric Engestrom2016-07-081-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Fix remaining flush vs invalidate race conditions in ↵Francisco Jerez2016-07-072-0/+27
| | | | | | | | | | | | | | | | | | | | | | | brw_emit_pipe_control_flush. This hardware race condition has caused problems several times already (see "i965: Fix cache pollution race during L3 partitioning set-up.", "i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs." and "i965: intel_texture_barrier reimplemented"). The problem is that whenever we attempt to both flush and invalidate multiple caches with a single pipe control command the flush and invalidation happen in reverse order, so the contents flushed from the R/W caches aren't guaranteed to become visible from the invalidated caches after the PIPE_CONTROL command completes execution if some concurrent rendering workload happened to pollute any of the invalidated R/O caches in the short window of time between the invalidation and flush. This makes sure that brw_emit_pipe_control_flush() has the effect expected by most callers of making the contents flushed from any R/W caches visible from the invalidated R/O caches. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make room in the batch epilogue for three more pipe controls.Francisco Jerez2016-07-072-10/+10
| | | | | | | | | Review carefully, it sucks to have to keep track of the number of command packet dwords emitted in the batch epilogue manually. The MI_REPORT_PERF_COUNT_BATCH_DWORDS calculation was obviously wrong. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+10
| | | | | | | | | There were two places in the driver doing a pipe control VF cache flush, one of them was missing this workaround, move it down into brw_emit_pipe_control_flush to make sure we don't miss it again. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-074-35/+11
| | | | | | | | Shouldn't cause any functional changes at this point, but we have forgotten to apply this workaround several times in the past, make sure it doesn't happen again. Reviewed-by: Alejandro Piñeiro <[email protected]>
* egl: restrict swap_available dri2_egl_display field to X11Frank Binns2016-07-072-3/+1
| | | | | | | This field is only ever set and read by the X11 platform. Signed-off-by: Frank Binns <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* egl: Fix the bad surface attributes combination checking for pbuffers. (v3)Guillaume Charifi2016-07-071-21/+15
| | | | | | | | | | | | | | | | | Fixes a regression induced by commit a0674ce5c41903ccd161e89abb149621bfbc40d2: When EGL_TEXTURE_FORMAT and EGL_TEXTURE_TARGET were both specified (and both != EGL_NO_TEXTURE), an error was instantly triggered, before the other one had even a chance to be checked, which is obviously not the intended behaviour. v2: Full commit hash, remove useless variables. v3: [chadv] Add Fixes footers. Fixes: piglit "spec/egl 1.4/eglcreatepbuffersurface and then glclear" Fixes: piglit "spec/egl 1.4/largest possible eglcreatepbuffersurface and then glclear" Signed-off-by: Guillaume Charifi <[email protected]> Reviewed-by: Frank Binns <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* egl/display: remove unnecessary code and make it easier to readEric Engestrom2016-07-071-15/+14
| | | | | | | | | Remove the two first level `if` as they will always be true, and flatten the two remaining `if`. No functional change. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: Make single-buffered GLES representation internally consistentGurchetan Singh2016-07-073-2/+30
| | | | | | | | | | | | | There are a few places in the code where clearing and reading are done on incorrect buffers for GLES contexts. See comments for details. This fixes 75 GLES3 dEQP tests on the surfaceless platform with no regressions. v2: Corrected unclear comment v3: Make the change in context.c instead of get.c v4: Removed whitespace Reviewed-by: Stéphane Marchesin <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* bugzilla_mesa.sh: Drop "Bug " from sed commandEmil Velikov2016-07-071-1/+1
| | | | | | | | After a recent Bugzilla update the word is no longer in the title. Thus the script ended up producing bogus HTML. Cc: "11.2 12.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* mesa: don't install GLX files if GLX is not builtAkihiko Odaki2016-07-072-0/+5
| | | | | | | Cc: "11.2 12.0" <[email protected]> Signed-off-by: Akihiko Odaki <[email protected]> [Emil Velikov: Drop guards around dri_interface.h, add stable tag] Signed-off-by: Emil Velikov <[email protected]>
* nir: add glsl_dvec_type() helperTimothy Arceri2016-07-062-0/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* osmesa: Export OSMesaCreateContextAttribs.Mathias Fröhlich2016-07-074-0/+4
| | | | | | | | | | | Since the function is exported like any other public api function and put in the header as if you could link against it, export it also from shared objects. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "11.2 12.0" <[email protected]>
* i965: consolidate generation checkTimothy Arceri2016-07-071-6/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: don't copy VS attribute work arounds for HSW+Timothy Arceri2016-07-071-2/+4
| | | | | | | These workarounds are not required for HSW and above so stop copying them at VS key generation which is called at draw time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double packing support to tess stagesTimothy Arceri2016-07-071-9/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double support packing support to gs inputsTimothy Arceri2016-07-071-2/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add glsl_double_type() helperTimothy Arceri2016-07-072-0/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support to gs load inputsTimothy Arceri2016-07-071-3/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support for tcs and tesTimothy Arceri2016-07-071-4/+29
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tcsTimothy Arceri2016-07-071-3/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tesTimothy Arceri2016-07-071-5/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for gsTimothy Arceri2016-07-072-5/+19
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: use the same driver location for packed varyingsTimothy Arceri2016-07-075-9/+38
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add new intrinsic field for storing component offsetTimothy Arceri2016-07-074-6/+23
| | | | | | This offset is used for packing. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/docs: update Intel Linux Graphics URLsEric Engestrom2016-07-064-4/+4
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* anv: gitignore anv_timestamp.hChad Versace2016-07-061-0/+1
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* radeon/llvm: Use alloca instructions for larger arraysTom Stellard2016-07-062-25/+151
| | | | | | | | | | | | | | | | | | | | We were storing arrays in vectors, which was leading to some really bad spill code for large arrays. allocas instructions are a better fit for arrays and LLVM optimizations are more geared toward dealing with allocas instead of vectors. For arrays that have 16 or less 32-bit elements, we will continue to use vectors, because this will force LLVM to store them in registers and use indirect registers, which is usually faster for small arrays. In the future we should use allocas for all arrays and teach LLVM how to store allocas in registers. This fixes the piglit test: spec/glsl-1.50/execution/geometry/max-input-component Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add helpers for loading and storing data from arrays.Tom Stellard2016-07-061-10/+41
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Remove uses_temp_indirect_addressing() functionTom Stellard2016-07-061-23/+1
| | | | | | bld->indirect_files is never set, so this function always returns false. Reviewed-by: Marek Olšák <[email protected]>
* anv: vulkan: remove the anv_device.$(OBJEXT) ruleEmil Velikov2016-07-062-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Atm the actual rule will expand to foo.o which is used for static libraries only. Thus the automake manual recommendation [to use OBJEXT] won't help us, since since we're working with a shared library. Thus let's 'demote' the file and add it back to BUILT_SOURCES. This will manage all the complexity for us, at the (existing expense) of working only with the all, check and install targets. The crazy (why the issue was hard to spot): If the dependencies (.deps/*.Plo) are already created one can alter the anv_device.$(OBJEXT) line and/or nuke it all together. That won't lead to any warnings/issues, even though the Makefile is regenerated. Moral of the story: Always rm -rf top_builddir or don't resolve the dependencies manually and use BUILT_SOURCES. Cc: "12.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96825 Fixes: d7a604c3f7a ("anv: use cache uuid based on the build timestamp.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Mark Janes <[email protected]>
* vbo: fix attr resetRob Clark2016-07-063-7/+10
| | | | | | | | | | | | | | | In bc4e0c4 (vbo: Use a bitmask to track the active arrays in vbo_exec*.) we stopped looping over all the attributes and resetting all slots. Which exposed an issue in vbo_exec_bind_arrays() for handling GENERIC0 vs. POS. Split out a helper which can reset a particular slot, so that vbo_exec_bind_arrays() can re-use it to reset POS. This fixes an issue with 0ad (and possibly others). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* list: fix list_replace() for empty listsRob Clark2016-07-061-4/+10
| | | | | | | | | Before, it would happily copy list_head next/prev (ie. pointer to the *from* list_head), leaving things in a confused state and causing much mayhem. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* gallium: un-inline pipe_surface_descRob Clark2016-07-061-11/+12
| | | | | | | Want to re-use this struct, so un-inline it. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: make util_copy_framebuffer_state(src=NULL) workRob Clark2016-07-061-11/+26
| | | | | | | | Be more consistent with the other u_inlines util_copy_xyz_state() helpers and support NULL src. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: avoid flushed depth when possibleNicolai Hähnle2016-07-061-3/+8
| | | | | | | If a depth/stencil texture has no mipmaps, we can always get a layout that is compatible with DB and TC. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add depth/stencil_adjusted output to surface computationNicolai Hähnle2016-07-063-2/+14
| | | | | | | | | | | This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga, though it's basically a function of the memory configuration so could affect other parts as well. Fixes piglit "unaligned-blit * stencil downsample" and various "fbo-depth-array *stencil*" tests. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: allocate only the required plane for flushed depthNicolai Hähnle2016-07-061-3/+34
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: decompress to flushed depth texture when requiredNicolai Hähnle2016-07-061-29/+103
| | | | | | v2: s/dirty_level_mask/stencil_dirty_level_mask/ in stencil case Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract DB->CB copy logic into its own functionNicolai Hähnle2016-07-061-36/+61
| | | | | | Also clean up some of the looping. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: sample from flushed depth texture when requiredNicolai Hähnle2016-07-062-8/+46
| | | | | | | Note that this has no effect yet. A case where can_sample_z/s can be false in radeonsi will be added in a later patch. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: replace is_flushing_texture with db_compatibleNicolai Hähnle2016-07-069-19/+24
| | | | | | | | | | | This is a left-over of when I considered generalizing the separate stencil support. I do prefer the new name since it emphasizes what flushing vs. non-flushing means from a functional point-of-view, namely special handling of the texture format. v2: adjust r600_init_color_surface as well Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add can_sample_z/s flags for texturesNicolai Hähnle2016-07-065-24/+34
| | | | | | v2: adjust r600_init_color_surface as well Reviewed-by: Marek Olšák <[email protected]>
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