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* svga: move assertion in draw_vgpu10()Brian Paul2017-07-031-1/+1
| | | | | | | The buffer binding flags aren't ensured until after the svga_buffer_handle() call, so move the assertion after it. Reviewed-by: Charmaine Lee <[email protected]>
* svga: fix buffer binding flags initializationBrian Paul2017-07-031-0/+6
| | | | | | | | | | | | | | | | | | | If a buffer is created/initialized with glNamedBufferData we will have no target (GL_ARRAY_BUFFER, GL_UNIFORM_BUFFER, etc) so the svga_buffer::bind_flags will be zero until we try to get the buffer handle. This patch initializes the svga_buffer::bind_flags field when it's zero. This fixes the Piglit arb_uniform_buffer_object-rendering-dsa test. Note that there's still issues in this area that'll have to be addressed in the future. For example, creating a buffer object as GL_UNIFORM_BUFFER and later using it as a vertex buffer will fail. Reviewed-by: Charmaine Lee <[email protected]>
* docs: update bug reporting guidelinesBrian Paul2017-07-031-1/+4
| | | | | Suggest attaching output of glxinfo/wglinfo. Suggest providing an apitrace.
* st/mesa: remove an obsolete commentNicolai Hähnle2017-07-031-1/+0
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* mesa: remove unused parameter/member of add_uniform_to_shaderNicolai Hähnle2017-07-031-6/+3
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util/disk_cache: fix a commentNicolai Hähnle2017-07-031-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* glsl: simplify disable_varying_optimizations_for_ssoNicolai Hähnle2017-07-031-18/+11
| | | | | | | | | We always have stage == first and stage == last when first == last, so drop the special case. Also rephrase the comment to make the logic clearer. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: always print non-zero var->data.location_fracNicolai Hähnle2017-07-031-1/+1
| | | | | | | This is helpful in debugging varying assignments. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* winsys/radeon: only call pb_slabs_reclaim when slabs are actually usedNicolai Hähnle2017-07-031-1/+2
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100242 Fixes: fb827c055cb1 ("winsys/radeon: enable buffer allocation from slabs") Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* anv: check support for enabled features in vkCreateDevice()Samuel Iglesias Gonsálvez2017-07-031-0/+13
| | | | | | | | | | | From Vulkan spec, 4.2.1. "Device Creation": "vkCreateDevice verifies that extensions and features requested in the ppEnabledExtensionNames and pEnabledFeatures members of pCreateInfo, respectively, are supported by the implementation." Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: merge tessellation's primitive mode in merge_tess_info()Samuel Iglesias Gonsálvez2017-07-031-0/+4
| | | | | | | | | | | | SPIR-V tessellation shaders that were created from HLSL will have the primitive generation domain set in tessellation control shader (hull shader in HLSL) instead of the tessellation evaluation shader. v2: - Add assert (Kenneth) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swr: Limit memory held by defer deleted resources.Bruce Cherniak2017-07-021-0/+6
| | | | | | | | | | | | | | | | | | | | | This patch limits the number of items on the fence work queue (the deferred deletion list) by submitting a sync fence when the queue size exceeds a threshold. This initiates deferred deletion of all resources on the list and decreases the total amount of memory held waiting for "deferred deletion". This resolves bug 101467 filed against swr for the piglit streaming-texture-leak test. For those running on smaller memory (16GB?) systems, this will prevent oom-killer. Thus far, we have not seen any real world applications that exhibit behavior like the streaming-texture-leak test; as any form of pipeline flush will trigger the defer queue and properly free any retained allocations. But, this addresses those as well. Cc: "17.1" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* anv: fix reported timestampPeriod valueLionel Landwerlin2017-07-021-1/+1
| | | | | | | | | | | We lost some precision on a previous change due to switching to integers. Since we report a float in timestampPeriod, we want the division to happen in floats. CID: 1413021 Fixes: c77d98ef32 ("intel: common: express timestamps units in frequency") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-026-45/+47
| | | | | | | In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* i965: Print access flags in INTEL_DEBUG=buf output.Kenneth Graunke2017-07-011-3/+22
| | | | | | | | | | | | | | | | | Being able to see the access mode of various mappings is incredibly useful for debugging. With this patch, INTEL_DEBUG=buf now shows data such as: bo_create: buf 7 (bufferobj) 640b bo_map_gtt: 7 (bufferobj) -> 0x7fca1fae5000, WRITE ASYNC brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ bo_map_gtt: 5 (bufferobj) -> 0x7fca1fad4000, WRITE ASYNC brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ which makes it easy to see that there are async GTT writes with intervening CPU reads. Reviewed-by: Matt Turner <[email protected]>
* i965: Remove clearing of bo->map_gtt after failureChris Wilson2017-07-011-1/+0
| | | | | | | | | | | | With the conversion to storing the result of drm_mmap to a local and not directly to bo->map_gtt itself, we no longer should clear bo->map_gtt. In the best the operation is redundant as we know bo->map_gtt to already be NULL, but in the worst case we overwrite a concurrent thread that successfully mmaped the GTT. Fixes: 314647c4c206 ("i965: Drop global bufmgr lock from brw_bo_map_* functions.") Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add inline to brw_bo_unmapKenneth Graunke2017-06-301-1/+1
| | | | | I meant to do this in "i965: Make brw_bo_unmap a static inline." but botched the commit fixup.
* i965: Drop global bufmgr lock from brw_bo_map_* functions.Chris Wilson2017-06-301-14/+15
| | | | | | | | | | | | After removing the unusuable debugging code in the previous commit, we can also entirely remove the global mutex around mapping the buffer for the first time and replace it with a single atomic operation to update the cache once we retrieve the mmap. v2 (Ken): Split out from Chris's original commit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make brw_bo_unmap a static inline.Kenneth Graunke2017-06-302-7/+1
| | | | | | | | | | | With the broken debugging code gone, it doesn't do anything anymore. We could technically eliminate it, but I'd like to keep it around in case we want to add something there again someday. Otherwise we'd have to go all over the codebase adding unmap calls back again. Based on a patch by Chris Wilson. Reviewed-by: Matt Turner <[email protected]>
* i965: Discard bo->map_countChris Wilson2017-06-302-53/+3
| | | | | | | | | | | | | | | Supposedly we were keeping a reference count for the number of users of a mapping so that we could use valgrind to detect access to the map outside of the valid section. However, we were incrementing the counter only when first creating the cached mapping but decrementing on every unmap. The bo->map_count tracking was wrong and so the debugging code was completely useless. v2 (Ken): Separate out atomic compare and swap optimization. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a comment about not needing VALGRIND_MALLOCLIKE_BLOCK.Kenneth Graunke2017-06-301-1/+3
| | | | | | | | | At first glance this seems missing, since we handle it manually for CPU and WC maps. Although a bit inconsistent, it's actually not necessary. Thanks to Chris Wilson for explaining this to me. Reviewed-by: Matt Turner <[email protected]>
* radv: Use v4i32 variant of llvm.SI.load.const.Bas Nieuwenhuizen2017-06-301-3/+1
| | | | | | | | | | We apparently still used v16i8 .... As radeonsi doesn't use it with LLVM version checks I don't think we need them either. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* svga: add texture size/levels sanity check code in svga_texture_create()Brian Paul2017-06-301-0/+33
| | | | | | | | | The state tracker should never ask us to create a texture with invalid dimensions / mipmap levels. Do some assertions to check that. No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* st/mesa: fix texture image resource selection in st_render_texture()Brian Paul2017-06-301-1/+18
| | | | | | | | | | | | | | If we're rendering to an incomplete/inconsistent (cube) texture, the different faces/levels of the texture may be stored in different resources. Before, we always used the texture object resource. Now, we use the texture image resource. In normal circumstances, that's the same resource. But in some cases, such as the Piglit fbo-incomplete-texture-03 test, the cube faces are in different resources and we need to render to the texture image resource. Fixes fbo-incomplete-texture-03 with VMware driver. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: check for incomplete texture in st_finalize_texture()Brian Paul2017-06-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Return early from st_finalize_texture() if we have an incomplete texture. This avoids trying to create a texture resource with invalid parameters (too many mipmap levels given the base dimension). Specifically, the Piglit fbo-incomplete-texture-03 test winds up calling pipe_screen::resource_create() with width0=32, height0=32 and last_level=6 because the first five cube faces are 32x32 but the sixth face is 64x64. Some drivers handle this, but others (like VMware svga) do not (generates device errors). Note that this code is on the path that's usually not taken (we normally build consistent textures). No Piglit regressions. v2: only need to check for base-level completeness since that's what has to be consistent in order to specify the dimensions for a new gallium texture. Per Roland. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: document that TXF is used with PIPE_BUFFER resourcesBrian Paul2017-06-301-1/+2
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: clarify that samplers are not used with PIPE_BUFFER resourcesBrian Paul2017-06-301-0/+8
| | | | | | | | Commit 8aba778fa2cd98a0b5a7429d3c5057778a0c808c "st/mesa: don't set sampler states for TBOs" changed how texture buffer objects are handled. Document the new convention. Reviewed-by: Roland Scheidegger <[email protected]>
* vc4: Start using XML unpack functions in CL dump.Eric Anholt2017-06-305-19/+67
| | | | | | For now this is a no-op on the output, but it makes it clear that we've had weird things going on with things like V3D21_CLIPPER_Z_SCALE_AND_OFFSET.
* vc4: Replace a couple of magic numbers with #define usage.Eric Anholt2017-06-301-2/+2
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* vc4: Move rasterizer state packing to CSO creation time.Eric Anholt2017-06-304-29/+25
| | | | | | | | | | This gets our vc4_emit.c size back down a bit: before: 1020 0 0 1020 3fc src/gallium/drivers/vc4/.libs/vc4_emit.o after: 968 0 0 968 3c8 src/gallium/drivers/vc4/.libs/vc4_emit.o
* vc4: Convert the driver to emitting the shader record using pack macros.Eric Anholt2017-06-304-54/+100
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* vc4: Simplify pack header usageEric Anholt2017-06-304-35/+28
| | | | | | | | | | | | | Take the CL pointer in, which will be useful for enabling relocs. However, our code expands a bit more: before: 4449 0 0 4449 1161 src/gallium/drivers/vc4/.libs/vc4_draw.o 988 0 0 988 3dc src/gallium/drivers/vc4/.libs/vc4_emit.o after: 4481 0 0 4481 1181 src/gallium/drivers/vc4/.libs/vc4_draw.o 1020 0 0 1020 3fc src/gallium/drivers/vc4/.libs/vc4_emit.o
* vc4: Start using the pack header.Eric Anholt2017-06-304-51/+130
| | | | | | | | | | | | | This slightly inflates the size of the generated code, in exchange for getting us some convenient tools. before: 4389 0 0 4389 1125 src/gallium/drivers/vc4/.libs/vc4_draw.o 808 0 0 808 328 src/gallium/drivers/vc4/.libs/vc4_emit.o after: 4449 0 0 4449 1161 src/gallium/drivers/vc4/.libs/vc4_draw.o 988 0 0 988 3dc src/gallium/drivers/vc4/.libs/vc4_emit.o
* vc4: Introduce XML-based packet header generation like Intel's.Eric Anholt2017-06-3013-1/+1143
| | | | | | | | | | | | | | | I really liked this idea, as it should help with management of packet parsing tools like the CL dump. The python script is forked off of theirs because our packets are byte-based instead of dwords, and the changes to do so while avoiding performance regressions due to unaligned accesses were quite invasive. v2: Fix Android.mk paths, drop shebang for python script, fix overlap detection. Acked-by: Jason Ekstrand <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Tested-by: Rob Herring <[email protected]>
* swr: Minor cleanup of variable usage, no functional change.Bruce Cherniak2017-06-301-2/+2
| | | | | | | | | | In swr_update_derived, for consistency, index buffer validation should be using the p_draw_info copy "info" rather than referencing p_draw_info. No functional change. Reviewed-by: Tim Rowley <[email protected]>
* swr: use swr_query_result type instead of voidTim Rowley2017-06-302-3/+3
| | | | | | | | | Tag pStat field in swr_draw_context structure so gen_llvm_types.py can deal with the actual structure type instead of using void. Code cleanup, no functional change. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: increase number of possible draws in flightTim Rowley2017-06-301-1/+1
| | | | | | Increases performance of some large workloads on KNL by ~30%. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: move default split size from driver to rasterizerTim Rowley2017-06-302-5/+1
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Fix missing setup of psContext.pColorBufferTim Rowley2017-06-302-16/+14
| | | | | | Fixes render target read access from pixel shaders. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Switch intrinsic usage to SIMDLibTim Rowley2017-06-3030-2679/+6222
| | | | | | | | Switch from a macro-based simd intrinsics layer to a more C++ implementation, which also adds AVX512 optimizations to 128-bit and 256-bit SIMD. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* scons: allow .inl file extensionTim Rowley2017-06-301-1/+1
| | | | | | Intended for header files which are not meant to be included directly. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Fix unused variable warningsTim Rowley2017-06-301-6/+0
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Split rasterizer.cpp to improve compile timeTim Rowley2017-06-3010-1617/+1732
| | | | | | | Hardcode split to four files currently. Decreases swr build time on KNL by over 50%. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: gen_backends.py remove extraneous semicolonTim Rowley2017-06-301-1/+2
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Support dynamically sized vertex layoutTim Rowley2017-06-306-21/+49
| | | | | | | | | | | | | | | Each shader stage state (VS, TS, GS, SO, BE/CLIP) now has a vertexAttribOffset to specify the offset to the start of the general attribute section of the incoming verts for that stage. It is up to the driver to set this up correctly based on the active stages. All the shader stages use this value instead of VERTEX_ATTRIB_START_SLOT to offset to the incoming attributes. Only the vertex shader stage supports dynamic layout output currently. The other stages continue to expect the output to be the fixed layout slots as before. Will be enabling GS next. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: Split backend.cpp to improve compile timeTim Rowley2017-06-3013-1832/+2146
| | | | | | | Hardcode split to four files currently. Decreases swr build time on a quad-core by ~10%. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: gen_backends.py removal of commented debug printsTim Rowley2017-06-301-4/+1
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: gen_backends.py quote cleanupTim Rowley2017-06-301-8/+8
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* swr/rast: generators will create target directoriesTim Rowley2017-06-301-0/+7
| | | | Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
* docs: update calendar, add news item and link release notes for 17.1.4Andres Gomez2017-06-303-7/+8
| | | | Signed-off-by: Andres Gomez <[email protected]>
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