| Commit message (Collapse) | Author | Age | Files | Lines |
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I want to notice discrepancies when I diff -u between Mesa and the kernel.
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Disabling miptails fixed the buffer corruption happening in FBO
which use YF/YS tiled renderbuffer or texture as color attachment.
Spec recommends disabling mip tails only for non-mip-mapped surfaces.
But, without disabling miptails I couldn't get correct data out of
mipmapped YF/YS tiled surface.
We need better understanding of miptails before start using them.
For now this patch helps move things forward.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
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Patch sets the alignments for texture and renderbuffer surfaces.
V3: Make changes inside horizontal_alignment() and
vertical_alignment() (Topi)
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
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Makes no functional changes in the code.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
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This function will be utilised in later patches.
V2: Make both pointers constants (Topi)
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
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This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
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The surfaceless platform is for off-screen rendering only. Render node support
is required.
Only consider the render nodes. Do not use normal nodes as they require
auth hooks.
v3: change platform_null to platform_surfaceless
v4: make libdrm required for surfaceless
v5: remove modified include guards with defined(HAVE_SURFACELESS_PLATFORM)
v6: use O_CLOEXEC for drm fd
Signed-off-by: Haixia Shi <[email protected]>
Signed-off-by: Zach Reizner <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
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Previously when setting up the sample instruction for an indirect
sampler the vec4 backend was directly passing the pseudo opcode's
src0. However vec4_visitor::visit(ir_texture *) doesn't set the
texture operation's src0 -- it's left as BAD_FILE, which when
translated into a brw_reg gives the null register. In brw_SAMPLE,
gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and
sets the src0 appropriately. The indirect sampler case did not have a
call to gen6_resolve_implied_move().
The fs backend avoids this because the platforms that support dynamic
indexing of samplers (IVB+) have been converted to not use the
fake-MRF hack, and instead send from proper GRFs.
This patch makes it call gen6_resolve_implied_move before setting up
the indirect message. This is similar to what is done for constant
sampler numbers in brw_SAMPLE.
The Piglit tests for sampler array indexing didn't pick this up
because they were using a texture with a solid colour so it didn't
matter what texture coordinates were actually used. The tests have now
been changed to be more thorough in this commit:
http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7
With that patch the tests for gs and vs are currently failing on
Ivybridge, but this patch fixes them. There are no other changes to a
Piglit run on Ivybridge.
On Skylake the gs tests were failing even without the Piglit patch
because Skylake needs the source registers to work correctly in order
to send a message header to select SIMD4x2 mode.
(The explanation in the commit message is partially written by Matt
Turner)
Tested-by: Anuj Phogat <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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For tessellation.
v2: cleanup by Marek Olšák
Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Picked from the tessellation branch.
Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Tom Stellard <[email protected]>
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This reverts commit adee54f8269c5e9f4fde91d19f0e465afc8f14d8.
Further down in the GLSL ES 3.10 spec it say:
"If an array is declared as the last member of a shader storage block
and the size is not specified at compile-time, it is sized at run-time.
In all other cases, arrays are sized only at compile-time."
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
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Before 9b5e92f get_gl_override was called only once, but now it is
called for multiple APIs (GLES2, GL), version needs to be set always.
Signed-off-by: Tapani Pälli <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Martin Peres <[email protected]>
Tested-by: Martin Peres <[email protected]>
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This function was trying to align the width and height to a multiple
of the block size for compressed textures. It was using align_w/h as a
shortcut to get the block size as up until Gen9 this always happens to
match. However in Gen9+ the alignment values are expressed as
multiples of the block size so in effect the alignment values are
always 4 for compressed textures as that is the minimum value we can
pick. This happened to work for most compressed formats because the
block size is also 4, but for FXT1 this was breaking because it has a
block width of 8.
This fixes some Piglit tests testing FXT1 such as
spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats
Reviewed-by: Nanley Chery <[email protected]>
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The state tracker will pass through requests from buggy applications
which will have the buffer size larger than the max allowed (64k). Clamp
the size to 64k so that we don't get errors when uploading the constbuf
data.
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: "10.5 10.6" <[email protected]>
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One of the places we have to insert texbars is in situations where the
result of the tex gets overwritten by a different instruction (e.g. in a
conditional statement). However in some situations it can actually
appear as though the original tex itself is an overwriting instruction.
This can naturally never really happen, so just ignore the tex
instruction when it comes up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90347
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: "10.5 10.6" <[email protected]>
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Back in 2013, a patch was added (with 2 reviewers!) at the end of the
block to early exit the loop in this case, without noticing that the loop
already did. I added another early exit case, again without noticing, but
Rob caught me. Just drop the loop condition that apparently surprises
most of us, instead of leaving the end of the loop conspicuously not
exiting on success.
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
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This was part of gallium_egl, and we now have the normal libEGL Android
winsys support to handle it.
Reviewed-by: Emil Velikov <[email protected]>
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v2: Add a comment explaining why we link libmesa_glsl. Drop warning
option from freedreno. Add vc4 to the documentation for
BOARD_GPU_DRIVERS.
Reviewed-by: Emil Velikov <[email protected]>
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v2: Add a comment explaining why we link libmesa_glsl.
Reviewed-by: Emil Velikov <[email protected]>
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Reviewed-by: Emil Velikov <[email protected]>
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in case of glTexImage{1,2,3}D(). Texture has already been allocated
at this point and we have no data to upload. With out this patch,
with create_pbo = true, we end up creating a temporary pbo and then
uploading uninitialzed texture data.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Neil Roberts <[email protected]>
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After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch.
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
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Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
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Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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intel_miptree_map_movntdqa()
We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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OP_JOIN instructions are assumed to be flow instructions and mercilessly
casted to FlowInstruction.
This patch fixes an instance where an OP_JOIN is created as a plain
instruction. This can cause crashes in the ir printer.
[imirkin: add ->fixed = 1]
Reviewed-by: Ilia Mirkin <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
(cherry picked from commit 5d327b373531861f86a726db669b3d656f1b5f8d)
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Signed-off-by: Emil Velikov <[email protected]>
(cherry picked from commit 3b9cde5c8138fb5cc45c652f2a5c15c5fa222bd7)
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Initialize hardware stipple states on bound instead of on emission.
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Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.
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Utilize ilo_state_raster to avoid redundant state change.
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This will be needed by radeonsi.
Reviewed-by: Ilia Mirkin <[email protected]>
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Trivial.
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Most of this code could be removed if r600g used tgsi_shader_info.
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With most code replaced to ilo_state_*, what was left did not belong there
anymore.
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