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* nir/algebraic: Allow for flagging operations as being inexactJason Ekstrand2016-03-234-2/+26
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* nir/search: Propagate exactness into newly created expressionsJason Ekstrand2016-03-231-4/+5
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* nir/builder: Add a flag for setting exactJason Ekstrand2016-03-231-0/+9
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* nir: Add an "exact" bit to nir_alu_instrJason Ekstrand2016-03-233-0/+14
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* nir/clone: Export nir_variable_cloneJason Ekstrand2016-03-232-4/+13
| | | | Reviewed-by: Rob Clark <[email protected]>
* nir/clone: Expose nir_constant_cloneJason Ekstrand2016-03-232-4/+5
| | | | Reviewed-by: Rob Clark <[email protected]>
* nir: Fix whitespaceJason Ekstrand2016-03-231-1/+1
| | | | Reviewed-by: Rob Clark <[email protected]>
* docs: use latest libDRM versionBrian Paul2016-03-231-2/+1
| | | | Signed-off-by: Brian Paul <[email protected]>
* compiler/glsl: allow sequence op as a const expr in gles 1.0Lars Hamre2016-03-231-1/+3
| | | | | | | | | | | | | | | | | Allow the sequence operator to be a constant expression in GLSL ES versions prior to GLSL ES 3.0 Fixes the following piglit test: /all/spec/glsl-es-1.0/compiler/array-sized-by-sequence-in-parenthesis.vert This is similar to the logic from process_initializer() which performs the same check for constant variable initialization with sequence operators. v2: Fixed regression pointed out by Eduardo Lima Mitev Signed-off-by: Lars Hamre <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* radeonsi: fix out-of-bounds indexing of shader imagesNicolai Hähnle2016-03-231-1/+43
| | | | | | | | | | | | Results are undefined but may not crash. Without this change, out-of-bounds indexing can lead to VM faults and GPU hangs. Constant buffers, samplers, and possibly others will eventually need similar treatment to support GL_ARB_robust_buffer_access_behavior. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)Nicolai Hähnle2016-03-231-2/+12
| | | | | | | | | This fixes arb_shader_image_load_store-host-mem-barrier. v2: flush TC L2 for index buffers on <= CIK (Marek) Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add missing MemoryBarrier bits and some explanationsNicolai Hähnle2016-03-231-1/+24
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_BARRIER_STREAMOUT_BUFFERNicolai Hähnle2016-03-231-0/+1
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix 2D array MSAA failures since image support landedMarek Olšák2016-03-231-1/+2
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* i965/fs: Don't constant-fold RCPJason Ekstrand2016-03-221-15/+0
| | | | | | No shader-db changes on Broadwell Reviewed-by: Matt Turner <[email protected]>
* i965: Remove the RCP+RSQ algebraic optimizationsJason Ekstrand2016-03-222-22/+0
| | | | | | | | | NIR already has this optimization and it can do much better than the little peephole in the backend. No shader-db change on Haswell or Broadwell. Reviewed-by: Matt Turner <[email protected]>
* nir: Don't abs slt and friendsIan Romanick2016-03-221-0/+4
| | | | | | | No shader-db changes, but this is symmetric with the previous commit. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Don't abs the result of b2f or b2iIan Romanick2016-03-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the results below, 2 SIMD16 shaders in Trine are lost. G4X total instructions in shared programs: 4012279 -> 4011108 (-0.03%) instructions in affected programs: 116776 -> 115605 (-1.00%) helped: 339 HURT: 0 total cycles in shared programs: 84315862 -> 84313584 (-0.00%) cycles in affected programs: 1767232 -> 1764954 (-0.13%) helped: 274 HURT: 81 Ironlake total instructions in shared programs: 6399073 -> 6396998 (-0.03%) instructions in affected programs: 218050 -> 215975 (-0.95%) helped: 600 HURT: 0 total cycles in shared programs: 128892088 -> 128888810 (-0.00%) cycles in affected programs: 2867452 -> 2864174 (-0.11%) helped: 422 HURT: 137 Sandy Bridge total instructions in shared programs: 8462174 -> 8460759 (-0.02%) instructions in affected programs: 178529 -> 177114 (-0.79%) helped: 596 HURT: 0 total cycles in shared programs: 117542276 -> 117534098 (-0.01%) cycles in affected programs: 1239166 -> 1230988 (-0.66%) helped: 369 HURT: 150 Ivy Bridge total instructions in shared programs: 7775131 -> 7773410 (-0.02%) instructions in affected programs: 162903 -> 161182 (-1.06%) helped: 590 HURT: 0 total cycles in shared programs: 65759882 -> 65747268 (-0.02%) cycles in affected programs: 1004354 -> 991740 (-1.26%) helped: 467 HURT: 141 Haswell total instructions in shared programs: 7107786 -> 7106327 (-0.02%) instructions in affected programs: 140954 -> 139495 (-1.04%) helped: 590 HURT: 0 total cycles in shared programs: 64668028 -> 64655322 (-0.02%) cycles in affected programs: 967080 -> 954374 (-1.31%) helped: 452 HURT: 149 LOST: 2 GAINED: 0 Broadwell total instructions in shared programs: 8980029 -> 8978287 (-0.02%) instructions in affected programs: 197232 -> 195490 (-0.88%) helped: 715 HURT: 0 total cycles in shared programs: 70070448 -> 70055970 (-0.02%) cycles in affected programs: 975724 -> 961246 (-1.48%) helped: 471 HURT: 111 LOST: 2 GAINED: 0 Skylake total instructions in shared programs: 9115178 -> 9113436 (-0.02%) instructions in affected programs: 203012 -> 201270 (-0.86%) helped: 715 HURT: 0 total cycles in shared programs: 68848660 -> 68834004 (-0.02%) cycles in affected programs: 993888 -> 979232 (-1.47%) helped: 473 HURT: 116 LOST: 2 GAINED: 0 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Simplify 0 < fabs(a)Ian Romanick2016-03-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandy Bridge / Ivy Bridge / Haswell total instructions in shared programs: 8462180 -> 8462174 (-0.00%) instructions in affected programs: 564 -> 558 (-1.06%) helped: 6 HURT: 0 total cycles in shared programs: 117542462 -> 117542276 (-0.00%) cycles in affected programs: 9768 -> 9582 (-1.90%) helped: 12 HURT: 0 Broadwell / Skylake total instructions in shared programs: 8980833 -> 8980826 (-0.00%) instructions in affected programs: 626 -> 619 (-1.12%) helped: 7 HURT: 0 total cycles in shared programs: 70077900 -> 70077714 (-0.00%) cycles in affected programs: 9378 -> 9192 (-1.98%) helped: 12 HURT: 0 G45 and Ironlake showed no change. v2: Modify the comments to look more like a proof. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Simplify 0 >= b2f(a)Ian Romanick2016-03-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | This also prevented some regressions with other patches in my local tree. Broadwell / Skylake total instructions in shared programs: 8980835 -> 8980833 (-0.00%) instructions in affected programs: 45 -> 43 (-4.44%) helped: 1 HURT: 0 total cycles in shared programs: 70077904 -> 70077900 (-0.00%) cycles in affected programs: 122 -> 118 (-3.28%) helped: 1 HURT: 0 No changes on earlier platforms. v2: Modify the comments to look more like a proof. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Simplify i2b with negated or abs operandIan Romanick2016-03-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables removing ssa_201 and ssa_202 in sequences like: vec1 ssa_200 = flt ssa_199, ssa_194 vec1 ssa_201 = b2i ssa_200 vec1 ssa_202 = i2b -ssa_201 shader-db results: Sandy Bridge total instructions in shared programs: 8462257 -> 8462180 (-0.00%) instructions in affected programs: 3846 -> 3769 (-2.00%) helped: 35 HURT: 0 total cycles in shared programs: 117542934 -> 117542462 (-0.00%) cycles in affected programs: 20072 -> 19600 (-2.35%) helped: 20 HURT: 1 Ivy Bridge total instructions in shared programs: 7775252 -> 7775137 (-0.00%) instructions in affected programs: 3645 -> 3530 (-3.16%) helped: 35 HURT: 0 total cycles in shared programs: 65760522 -> 65760068 (-0.00%) cycles in affected programs: 21082 -> 20628 (-2.15%) helped: 25 HURT: 2 Haswell total instructions in shared programs: 7108666 -> 7108589 (-0.00%) instructions in affected programs: 3253 -> 3176 (-2.37%) helped: 35 HURT: 0 total cycles in shared programs: 64675726 -> 64675272 (-0.00%) cycles in affected programs: 21034 -> 20580 (-2.16%) helped: 26 HURT: 1 Broadwell / Skylake total instructions in shared programs: 8980912 -> 8980835 (-0.00%) instructions in affected programs: 3223 -> 3146 (-2.39%) helped: 35 HURT: 0 total cycles in shared programs: 70077926 -> 70077904 (-0.00%) cycles in affected programs: 21886 -> 21864 (-0.10%) helped: 21 HURT: 6 G45 and Ironlake showed no change. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Lower flrp with Boolean interpolator to bcselIan Romanick2016-03-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | On Intel platforms that don't set lower_flrp, using bcsel instead of flrp seems to be a small amount worse. On those platforms, the use of flrp, bcsel, and multiply of b2f is still an active area of research. In review, Matt suggested this is because bcsel turns into CMP+SEL, and because of the flag register we can't schedule instructions well. shader-db results: G4X / Ironlake total instructions in shared programs: 4016538 -> 4012279 (-0.11%) instructions in affected programs: 161556 -> 157297 (-2.64%) helped: 1077 HURT: 1 total cycles in shared programs: 84328296 -> 84315862 (-0.01%) cycles in affected programs: 4174570 -> 4162136 (-0.30%) helped: 926 HURT: 53 Unsurprisingly, no changes on later platforms. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Have NIR lower flrp on pre-GEN6 vec4 backendIan Romanick2016-03-221-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we were doing the lowering by hand in vec4_visitor::emit_lrp. By doing it in NIR, we have the opportunity for NIR to do additional optimization of the expanded code. This also enables optimizations added by the next commit. shader-db results: G4X / Ironlake total instructions in shared programs: 4024401 -> 4016538 (-0.20%) instructions in affected programs: 447686 -> 439823 (-1.76%) helped: 2623 HURT: 0 total cycles in shared programs: 84375846 -> 84328296 (-0.06%) cycles in affected programs: 16964960 -> 16917410 (-0.28%) helped: 2556 HURT: 41 Unsurprisingly, no changes on later platforms. v2: Formatting and comment changes suggested by Matt. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swrast: fix discarded const warning in s_texture.cBrian Paul2016-03-221-1/+1
| | | | Signed-off-by: Brian Paul <[email protected]>
* i965: fix invalid memory writeMarc-André Lureau2016-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed some heap corruption running virgl tests, and valgrind helped me to track it down to the following error: ==29272== Invalid write of size 4 ==29272== at 0x90283D4: push_loop_stack (brw_eu_emit.c:1307) ==29272== by 0x9029A7D: brw_DO (brw_eu_emit.c:1750) ==29272== by 0x90554B0: fs_generator::generate_code(cfg_t const*, int) (brw_fs_generator.cpp:1999) ==29272== by 0x904491F: brw_compile_fs (brw_fs.cpp:5685) ==29272== by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137) ==29272== by 0x8FC7663: brw_fs_precompile (brw_wm.c:638) ==29272== by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51) ==29272== by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260) ==29272== by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006) ==29272== by 0x8C84325: _mesa_link_program (shaderapi.c:1042) ==29272== by 0x8C851D7: _mesa_LinkProgram (shaderapi.c:1515) ==29272== by 0x4E4B8E8: add_shader_program (vrend_renderer.c:880) ==29272== Address 0xf2f3cb0 is 0 bytes after a block of size 112 alloc'd ==29272== at 0x4C2AA98: calloc (vg_replace_malloc.c:711) ==29272== by 0x8ED11F7: ralloc_size (ralloc.c:113) ==29272== by 0x8ED1282: rzalloc_size (ralloc.c:134) ==29272== by 0x8ED14C0: rzalloc_array_size (ralloc.c:196) ==29272== by 0x9019C7B: brw_init_codegen (brw_eu.c:291) ==29272== by 0x904F565: fs_generator::fs_generator(brw_compiler const*, void*, void*, void const*, brw_stage_prog_data*, unsigned int, bool, gl_shader_stage) (brw_fs_generator.cpp:124) ==29272== by 0x9044883: brw_compile_fs (brw_fs.cpp:5675) ==29272== by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137) ==29272== by 0x8FC7663: brw_fs_precompile (brw_wm.c:638) ==29272== by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51) ==29272== by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260) ==29272== by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006) if_depth_in_loop is an array of size p->loop_stack_array_size, and push_loop_stack() will access if_depth_in_loop[p->loop_stack_depth+1], thus the condition to grow the array should be p->loop_stack_array_size <= (p->loop_stack_depth + 1) (it's currently off by 2...) This can be reproduced by running the following test with virgl test server: LIBGL_ALWAYS_SOFTWARE=y GALLIUM_DRIVER=virpipe bin/shader_runner ./tests/shaders/glsl-fs-unroll-explosion.shader_test -auto Signed-off-by: Marc-André Lureau <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* tgsi: drop unused set_exec/kill_mask interfaces.Dave Airlie2016-03-223-37/+0
| | | | | | | | | These don't get used and haven't been in git history from what I can see, so drop them. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* docs/relnotes: update ARB_internalformat_query2 status.Dave Airlie2016-03-221-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: add support for internalformat query2.Dave Airlie2016-03-223-11/+46
| | | | | | | | Add code to handle GL_INTERNALFORMAT_PREFERRED. Add code to deal with GL_RENDERBUFFER being passes into ChooseTextureFormat. Reviewed-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Fix assert conditions for src/dst x/y offsetsAnuj Phogat2016-03-211-3/+3
| | | | | | Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: Move assert for 'slice' in to check_map_teximageAnuj Phogat2016-03-211-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* r600/sb: Do not distribute neg in expr_handler::fold_assoc() when folding ↵xavier2016-03-221-2/+6
| | | | | | | | | | | | | | | multiplications. Previously it was doing this transformation for a Trine 3 shader: MUL R6.x.12, R13.x.23, 0.5|3f000000 - MULADD R4.x.12, -R6.x.12, 2|40000000, 1|3f800000 + MULADD R4.x.12, -R13.x.23, -1|bf800000, 1|3f800000 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94412 Signed-off-by: Xavier Bouchoux <[email protected]> Cc: "11.0 11.1 11.2" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0: make sure to delete samplers used by compute shadersSamuel Pitoiset2016-03-211-1/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* i965/blorp: Make BlitFramebuffer() do sRGB encoding in ES 3.x.Kenneth Graunke2016-03-211-1/+4
| | | | | | | | | | | | | | | | | | According to the ES 3.0 and GL 4.4 specifications, glBlitFramebuffer is supposed to perform sRGB decoding and encoding whenever sRGB formats are in use. The ES 3.0 specification is completely clear, and has always stated this. However, the GL specification has changed behavior in 4.1, 4.2, and 4.4. The original behavior stated that no sRGB encoding should occur. The 4.4 behavior matches ES 3.0's wording. However, implementing the new behavior appears to break applications such as Left 4 Dead 2. This patch changes Meta to apply the ES 3.x rules in ES 3.x, but leaves OpenGL alone for now, to avoid breaking applications. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Refactor sRGB encoding/decoding.Kenneth Graunke2016-03-214-11/+23
| | | | | | | | | | | | Because the rules for sRGB are so insane, we change brw_blorp_miptrees to take decode_srgb and encode_srgb flags, which control linearization of the source and destination separately. This should make it easy to implement whatever crazy combination of rules people throw at us. For now, it should be equivalent. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* meta: Make BlitFramebuffer() do sRGB encoding in ES 3.x.Kenneth Graunke2016-03-213-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the ES 3.0 and GL 4.4 specifications, glBlitFramebuffer is supposed to perform sRGB decoding and encoding whenever sRGB formats are in use. The ES 3.0 specification is completely clear, and has always stated this. However, the GL specification has changed behavior in 4.1, 4.2, and 4.4. The original behavior stated that no sRGB encoding should occur. The 4.4 behavior matches ES 3.0's wording. However, implementing the new behavior appears to break applications such as Left 4 Dead 2. This patch changes Meta to apply the ES 3.x rules in ES 3.x, but leaves OpenGL alone for now, to avoid breaking applications. Meta implements several other functions in terms of BlitFramebuffer, and many of those explicitly do not perform sRGB encoding. So, this patch explicitly disables sRGB encoding in those other functions, preserving the existing (correct) behavior. If you're from the future and are reading this, hi! Welcome to the "fun" of debugging sRGB problems! Best of luck! Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* docs: mark GL_ARB_shader_image_load_store/_size as done for radeonsiNicolai Hähnle2016-03-212-2/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGESEdward O'Callaghan2016-03-211-1/+2
| | | | | | | | | This enables ARB_shader_image_load_store and ARB_shader_image_size. Signed-off-by: Edward O'Callaghan <[email protected]> [allow the same number of images for all shader stages and require LLVM 3.9] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: disable early Z if the fragment shader writes to memoryNicolai Hähnle2016-03-211-2/+12
| | | | | | Empirically, both the EXEC_ON_* flags and LATE_Z are necessary. Reviewed-by: Marek Olšák <[email protected]>
* tgsi/scan: add writes_memory to flag presence of stores or atomicsNicolai Hähnle2016-03-212-4/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: force the DCC enable bit off in image descriptors for writing (v2)Nicolai Hähnle2016-03-211-8/+49
| | | | | | | | This avoids a lockup at least on Tonga. v2: only force DCC off on VI+ (Marek) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement MemoryBarrier (v2)Nicolai Hähnle2016-03-211-0/+37
| | | | | | v2: invalidate both constant and VMEM/TC L1 for constant buffers (Marek) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement volatile memory accessNicolai Hähnle2016-03-211-0/+4
| | | | | | | | | | Prevent loads from being re-ordered or coalesced. Atomics don't need special handling by definition, and stores don't need special handling because LLVM is unable to detect dead image or buffer stores. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement coherent memory access (v2)Nicolai Hähnle2016-03-211-4/+13
| | | | | | v2: set glc=1 for volatile also on buffers Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lower TGSI_OPCODE_MEMBAR down to LLVM opNicolai Hähnle2016-03-211-0/+31
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM opNicolai Hähnle2016-03-211-8/+113
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lower TGSI_OPCODE_STORE down to LLVM opNicolai Hähnle2016-03-211-3/+80
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lower TGSI_OPCODE_LOAD down to LLVM op (v3)Nicolai Hähnle2016-03-211-0/+139
| | | | | | | v2: new signature style for buffer intrinsics (offsets) v3: new signature style for llvm.amdgcn.buffer.load.format (overloaded return) Reviewed-by: Marek Olšák <[email protected]> (v2)
* radeonsi: extract the LLVM type name construction into its own functionNicolai Hähnle2016-03-211-7/+19
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lower TGSI_OPCODE_RESQ down to LLVM opNicolai Hähnle2016-03-211-0/+129
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract TXQ buffer size computation into its own functionNicolai Hähnle2016-03-211-20/+35
| | | | | | This will allow it to be reused for RESQ. Reviewed-by: Marek Olšák <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 07:57:34 +0000