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* gallivm, tgsi: provide fake sample_i_ms implementationsRoland Scheidegger2016-02-182-4/+11
| | | | | | | Just like the rest of the msaa "implementation" it's just fake for now... Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: new st_DrawAtlasBitmaps() function for drawing bitmap textBrian Paul2016-02-172-3/+141
| | | | | | | | | | | | This basically saves the current pipeline state, sets up state for rendering, constructs a set of textured quads, renders, then restores the previous pipeline state. It shouldn't be hard to implement a similar function for non-gallium drives. With some code refactoring, the vertex definition code could probably be shared. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: implement a display list / glBitmap texture atlasBrian Paul2016-02-175-0/+448
| | | | | | | | | | | | | | | | | | | | | This improves the performance of applications which use glXUseXFont() or wglUseFontBitmaps() and glCallLists() to draw bitmap text. Basically, we collect all the glBitmap images from the display lists and put them into a texture atlas. To render the bitmaps for a glCallLists() command, we render a set of textured quads where each quad is textured with one bitmap image. Actually, the rendering part has to be done by the Mesa driver or Mesa/gallium state tracker. Note that GLUT demos that use glutBitmapCharacter() don't benefit from this. v2, per Nicolai Hähnle: - check the max tex rect size is at least 1024. - add comment in dd.h that texture_rectangle is required. - in _mesa_DeleteLists(), try to delete the atlas before the list(s) Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: apply DepthMode swizzle to stencil texturing as wellIlia Mirkin2016-02-171-2/+0
| | | | | | | | Gallium doesn't present these as GL_RED-style. A swizzle is necessary to present the proper data in the unused components. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965/skl: Update Skylake renderer stringsBen Widawsky2016-02-171-9/+9
| | | | | | | | | | Also adds some of the Iris/Pro parts which we previously didn't have named. v2: 0x192d is gt3, not gt4 Adding some 'e' tags for eDRAM parts Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* i965/skl: Add two missing device IDsBen Widawsky2016-02-171-0/+2
| | | | | | | | | | | | The Iris part is left unbranded because we did not have these with original SKL. v2: 0x192d is gt3, not gt4 v3: Forgot to update the temporary brand string when I did v2. Cc: "11.0 11.1" <[email protected] Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* mesa: allow multisampled format info to be returned on GLES 3.1Ilia Mirkin2016-02-171-1/+4
| | | | | | | | | | | | The restriction on multisampled integer texture formats only applies to GLES 3.0, so don't apply it to GLES 3.1 contexts. This fixes a slew of dEQP-GLES31.functional.state_query.internal_format.* tests, which now all pass. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Extract push constant state to a new fileBen Widawsky2016-02-174-164/+191
| | | | | | | | | | | Every stage has a corresponding 3DSTATE_CONSTANT_XS packet, so having the code to create and emit push constant buffers in genX_vs_state.c is a little strange. Moving it to a separate file seems more logical. v2 [Ken]: Rebase on master, explain motivation in the commit message. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make emit_minmax return an instruction*.Matt Turner2016-02-173-10/+10
| | | | And use it in brw_fs_nir.cpp.
* i965: Lower min/max after optimization on Gen4/5.Matt Turner2016-02-178-44/+88
| | | | | | | | | | | | | | | | | | | Gen4/5's SEL instruction cannot use conditional modifiers, so min/max are implemented as CMP + SEL. Handling that after optimization lets us CSE more. On Ironlake: total instructions in shared programs: 6426035 -> 6422753 (-0.05%) instructions in affected programs: 326604 -> 323322 (-1.00%) helped: 1411 total cycles in shared programs: 129184700 -> 129101586 (-0.06%) cycles in affected programs: 18950290 -> 18867176 (-0.44%) helped: 2419 HURT: 328 Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: Initialize force_writemask_all in vec4_builder().Matt Turner2016-02-171-1/+2
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* radeon/llvm: Add TargetLibraryInfo to the pass managerTom Stellard2016-02-171-1/+7
| | | | | | | | This will prevent optimization passes from introducing unsupported library calls. Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Set the target triple on the moduleTom Stellard2016-02-174-4/+12
| | | | | Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallivm: Add helpers for creating and destroying TargetLibraryInfoTom Stellard2016-02-172-0/+37
| | | | | | | This functionality is not exposed via the LLVM C API. Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: invalidate all buffers when switching pipe contextsSamuel Pitoiset2016-02-171-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix up result_src.type when doing i2u/u2i conversionsIlia Mirkin2016-02-171-0/+1
| | | | | | | | | | | | Even though it's a no-op, it's important to keep track of the type so that we can pick the properly-signed op later on. This fixes dEQP-GLES3.functional.shaders.precision.uint.highp_div_fragment, which ended up using IDIV instead of UDIV. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* st/mesa: use cso_set_viewport_dims() in try_pbo_upload_common()Brian Paul2016-02-171-12/+1
| | | | | | | Note that this results in a different transformation for the viewport's Z axis (depth range), but that doesn't matter for this case. Reviewed-by: Roland Scheidegger <[email protected]>
* i965/gen7: Use predicated rendering for indirect computeJordan Justen2016-02-172-14/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | On gen7 (Ivy Bridge, Haswell), we will get a GPU hang if an indirect dispatch is used, but one of the dimensions is 0. Therefore we use predicated rendering on the GPGPU_WALKER command to handle this case. Fixes piglit test: spec/arb_compute_shader/zero-dispatch-size From the ARB_compute_shader spec, under DispatchCompute: "If the work group count in any dimension is zero, no work groups are dispatched." And then for DispatchComputeIndirect: ... "is equivalent (assuming no errors are generated) to calling DispatchCompute with <num_groups_x>, <num_groups_y> and <num_groups_z>" ... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94100 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
* freedreno: expose time-elapsed queryRob Clark2016-02-172-1/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: implement time-elapsed queryRob Clark2016-02-172-0/+133
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: better occlusion/sample countingRob Clark2016-02-171-1/+6
| | | | | | | | | | This seems to give more reliable results. More similar to what we do on a3xx, although I think it breaks the a3xx theory that the four sets of results map to each MRT (since we appear to still only have four sets on a4xx). The divide-by-two is a bit odd, but seems to be needed for some reason. Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: fix refcnt'ing issueRob Clark2016-02-171-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: some queries don't have ->begin_query()Rob Clark2016-02-172-0/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: align counter snapshot locationsRob Clark2016-02-171-0/+2
| | | | | | | | | | | | Some hw queries need their sample memory locations to have certain alignment. At the moment that isn't an issue, since the only hw query is occlusion, so all samples have the same size. But when others are added with different sample sizes, this starts to be a problem. All current and immediately upcoming hw queries simply need their sample address aligned to their size, so let's use that for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: add optional enable hookRob Clark2016-02-175-0/+36
| | | | | | | | Add enable hook for hw query providers. Some will need to configure perfctr selector registers, which we want to do at the start of the submit. Signed-off-by: Rob Clark <[email protected]>
* freedreno: query max gpu freqRob Clark2016-02-173-1/+12
| | | | | | | | This will be needed to support converting from cycle counts to time for performance related queries (initially time-elapsed, but there are some additional performance counters that could be wired up). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-02-175-30/+1355
| | | | | | Mostly to pull in perf ctrs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix new gcc6 errorsRob Clark2016-02-171-1/+0
| | | | | | | | | | | | | | | | src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c: In function ‘emit_tex’: src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c:1368:26: warning: unused variable ‘const_off’ [-Wunused-variable] struct ir3_instruction *const_off[4]; ^~~~~~~~~ unused since: commit 8750299a420af76cebd3067f6f603eacde06ae06 Author: Jason Ekstrand <[email protected]> Date: Tue Feb 9 14:51:28 2016 -0800 nir: Remove the const_offset from nir_tex_instr Signed-off-by: Rob Clark <[email protected]>
* nv50/ir: we can't do the add to mad conversion when the mul saturatesKarol Herbst2016-02-161-0/+3
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize neg(and(set, 1)) to setKarol Herbst2016-02-161-0/+32
| | | | | | | | | | | | | | | | | | | helps shaders in saints row IV, bioshock infinite and shadow warrior total instructions in shared programs : 1914931 -> 1903900 (-0.58%) total gprs used in shared programs : 247920 -> 247785 (-0.05%) total local used in shared programs : 5673 -> 5673 (0.00%) total bytes used in shared programs : 17558272 -> 17457320 (-0.57%) local gpr inst bytes helped 0 137 719 719 hurt 0 12 0 0 v2: remove this opt for OP_SLCT and check against float for OP_SET v3: simplified the code Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix quadop emission in the presence of predicationIlia Mirkin2016-02-164-5/+9
| | | | | | | | | | | | When there's a predicate, it just goes onto the sources list. If the quadop only has a single regular source, we will end up thinking that the predicate is the second source. Check explicitly for the predSrc so that we don't accidentally emit the wrong thing. This fixes a bunch of dEQP-GLES3.functional.shaders.derivate.* tests. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50,nvc0: enable/disable seamless cubemap texturing as requestedIlia Mirkin2016-02-1612-3/+26
| | | | | | | | | | In a situation where the seamless setting isn't available on a per-texture basis (G200+ Teslas, and all Fermis), assume that all samplers will have it identically set, and enable accordingly. This fixes arb_seamless_cubemap piglit test on Fermi and Tesla. Signed-off-by: Ilia Mirkin <[email protected]>
* st/mesa: add missing ETC2 entries to format_mapRob Clark2016-02-161-0/+42
| | | | | | | | Noticed by Ilia when I was trying to figure out why some app was failing to use ETC2. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: enable compute support on GK110:GM200 with an envvarSamuel Pitoiset2016-02-161-2/+7
| | | | | | | | | | | | | Without this NVF0_COMPUTE environment variable, compute support is initialized by default and this is not what we want for now because it might break 3D. It will be enabled by default once we are sure it won't break anything. Please note that compute support on GM200+ is not enabled yet because it needs to be double-checked. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add compute support for GM107Samuel Pitoiset2016-02-162-1/+5
| | | | | | | | Fortunately, compute support on GM107 is very close to GK110, except the GK110_COMPUTE.UNK02C4 which is invalid and should not be used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix compute state initialization on GK110+Samuel Pitoiset2016-02-161-6/+7
| | | | | | | | | | | Because our firmware doesn't support the GK110_COMPUTE.FIRMWARE[0x6] method the GPU hangs when it is used. Removing it fix the issue and allow to launch compute shaders on GK110+. Tested on GK208 and GM107. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: remove duplicate interpolation_string() functionTimothy Arceri2016-02-173-30/+2
| | | | | | | We already have one in the IR code that can be used everywhere its needed in the AST code so remove the one from the AST. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: remove unused helperTimothy Arceri2016-02-172-26/+0
| | | | | | Seems to have become unused when i965 moved to NIR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl: set user defined varyings to smooth by default in ESTimothy Arceri2016-02-171-0/+11
| | | | | | | | | | | | | | | | This is usually handled by the backends in order to handle the various interactions with the gl_*Color built-ins. The problem is this means linking will fail if one side on the interface adds the smooth qualifier to the varying and the other side just uses the default even though they match. This fixes various deqp tests. The spec is not clear what to for desktop GL so leave it as is for now. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92743
* gm107/ir: add ATOM CAS emissionSamuel Pitoiset2016-02-161-15/+27
| | | | | | | | | This fixes the following dEQP test and the other compswap variants. dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: do not init limits when compute shaders are not supportedSamuel Pitoiset2016-02-161-0/+8
| | | | | | | | | | | | | | | | | When the number of uniform blocks is less than 12, ARB_uniform_buffer_object can't be enabled and the maximum GL version is not even 3.1... This fixes a regression introduced in 7c79c1e (st/mesa: add compute shader state) if the maximum number of uniform blocks allowed for compute shaders is less than 12. This happens on Kepler but this might also affect other Gallium drivers. Signed-off-by: Samuel Pitoiset <[email protected]> Reported-by: Tobias Klausmann <[email protected]> Tested-by: Tobias Klausmann <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]>
* mesa: Don't call driver when there is no compute workJordan Justen2016-02-161-0/+3
| | | | | | | | | | The ARB_compute_shader spec says: "If the work group count in any dimension is zero, no work groups are dispatched." Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965: Set compute shader shared memory max to 64kJordan Justen2016-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | See Ivy Bridge PRM, Volume 2, Part 2, 1.8.4 INTERFACE_DESCRIPTOR_DATA: DWORD 5, bits 20:16: "This field indicates how much shared local memory the thread group requires. The amount is specified in 4k blocks, but only powers of 2 are allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice." For Haswell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA: DWORD 5, bits 20:16: With text identical to the Ivy Bridge PRM. For Broadwell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA: DWORD 6, bits 20:16: With text identical to the Ivy Bridge PRM. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* st/mesa: use new CSO_BITS_ALL_SHADERSBrian Paul2016-02-164-24/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* cso: add CSO_BITS_ALL_SHADERSBrian Paul2016-02-161-0/+6
| | | | | | For saving/restoring all shader stages. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: simplify st->ctx, ctx->st usage in a various placesBrian Paul2016-02-166-18/+17
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* st/mesa: use _mesa_geometric_width/height() in glDrawPixels codeBrian Paul2016-02-161-10/+9
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: rename attr variable in st_DrawTex()Brian Paul2016-02-161-10/+10
| | | | | | | Rename to 'tex_attr' to be a bit more clear. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: use 'cso' instead of 'st->cso_context' in st_DrawTex()Brian Paul2016-02-161-1/+1
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: fix whitespace and add comment in st_DrawTex()Brian Paul2016-02-161-3/+3
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
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