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* vc4: Remove dead fields from vc4_surface.Eric Anholt2015-04-131-3/+0
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* vc4: Skip sending down the clear colors if not clearing.Eric Anholt2015-04-131-5/+7
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* vc4: Sync with kernel changes to relax BCL versus RCL validation.Eric Anholt2015-04-131-22/+3
| | | | There was no reason to tie the two packets' values together.
* vc4: Fix another space allocation mistake.Eric Anholt2015-04-131-0/+1
| | | | | | We're over-allocating our BCL in vc4_draw.c, so this never mattered. However, new RCL-only blit support might end up here without having set up any BCL contents.
* vc4: Add missed accounting for the size of the semaphore.Eric Anholt2015-04-131-0/+2
| | | | This wouldn't have mattered except in the worst case scenario RCL setup.
* swrast: Mark MAX_GLUINT literal with u suffix.Matt Turner2015-04-131-1/+1
| | | | | | | | Coverity is confused by the "float < int / 2" expression and suggests casting MAX_GLUINT to unsigned, which I believe it was supposed to have been already. Reviewed-by: Brian Paul <[email protected]>
* i965: Don't bother freeing NULL.Matt Turner2015-04-131-4/+2
| | | | | | | Commit e16c5c90 was replacing 'region' with 'mt', leaving this nonsensical code. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Lift some restrictions on dma_buf EGLImagesChad Versace2015-04-133-22/+7
| | | | | | | | | | | | | | | | | | | | | Allow glEGLImageTargetRenderbufferStorageOES and glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is a single RGBA8 unorm plane. This is safe, despite fast color clears, because i965 disables allocation of auxiliary buffers for EGLImages. Chrome OS needs this, because its compositor uses dma_buf EGLImages for its scanout buffers. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`, with my Piglit patches that update the EGL_EXT_image_dma_buf_import tests. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disable aux buffers for EGLImage-backed miptreesChad Versace2015-04-132-5/+19
| | | | | | | | | | | | | | | | | | | | EGL does not yet have extensions to manage the flushing and invalidating of driver-internal aux buffers. So we must disable aux buffers of dma_buf-backed EGLImages in order to safely render into them. This patch is obviously needed for renderbufers. It's also needed for textures because the user can attach the texture to a framebuffer and because the driver sometimes renders to textures for internal reasons. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-136-11/+21
| | | | | | | | | | | Add parameter 'bool disable_aux_buffers'. This is a refactor patch. The patch changes no behavior because the new parameter is false in every call. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add field intel_mipmap_tree::disable_aux_buffersChad Versace2015-04-132-2/+29
| | | | | | | | | | | | | | | | | | | | | | The new field disables allocation of auxiliary buffers, such as the HiZ buffer and MCS buffer. This is useful for sharing the miptree bo with an external client that doesn't understand auxiliary buffers. We need this field to safely render to a buffer that was imported with EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions to manage flushing and invalidating auxiliary buffers. Nothing yet enables this field. That's left to follow-up patches. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-135-25/+30
| | | | | | | | | | | | | | | | | | | | | Every caller of this function uses it to determine if the current miptree needs a hiz buffer to be allocated. Strangely, the function doesn't take a miptree argument. So, this function effectively decides if and when a miptree's hiz buffer gets allocated without inspecting the miptree itself. Luckily, the driver behaves correctly despite the brw_is_hiz_depth_format's quirk. I will soon make some changes to the miptree that will require inspecting the miptree to determine if it needs a hiz buffer. So this patch renames brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer and gives it a miptree parameter. This patch shouldn't change any behavior. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Declare intel_miptree_create_layout() as staticChad Versace2015-04-132-14/+1
| | | | | | | | It's not used outside intel_mipmap_tree.c. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Declare intel_miptree_alloc_mcs() as staticChad Versace2015-04-132-6/+6
| | | | | | | | It's not used outside of intel_mipmap_tree.c, nor should it ever be. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* docs: Improve LLVM_USE_CRT_xxx instructions.Jose Fonseca2015-04-131-5/+27
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* glx: Include util/macros.h instead of redefining PRINTFLIKE.Jose Fonseca2015-04-131-6/+1
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* util/ralloc: Fix `extern "C"` usage.Jose Fonseca2015-04-131-4/+4
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.Jose Fonseca2015-04-132-9/+1
| | | | | | | I'm not sure what was the original intention, but currently USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another. Reviewed-by: Roland Scheidegger <[email protected]>
* docs: add news item and link release notes for mesa 10.5.3Emil Velikov2015-04-122-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add 256 sums for the 10.5.3 releaseEmil Velikov2015-04-121-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 65776421fe59a0ffd5388c0968c9b0b1c1b230ed)
* Add release notes for the 10.5.3 releaseEmil Velikov2015-04-121-0/+124
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit c4b8bff6e24c6661a8a05ec05f8ed5762e95021b)
* docs: remove the --with-max-{width,height} noteEmil Velikov2015-04-121-13/+0
| | | | | | | | Missed out with commit d99135b2e9b(configure: nuke --with-max-{width,height}) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* configure.ac: remove deprecated --with-libclc-pathEmil Velikov2015-04-121-13/+0
| | | | | | | | | The option was deprecated with commit 959e83d6507(clover: Adapt libclc's INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.) back in 2012 with mesa 9.2. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* i965/nir: Make INTEL_DEBUG=ann work with NIR.Kenneth Graunke2015-04-112-1/+8
| | | | | | | | | Now that we store a copy of the NIR shader, and don't immediately free it, we can use it in annotations as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Create NIR during LinkShader() and ProgramStringNotify().Kenneth Graunke2015-04-119-176/+257
| | | | | | | | | | | | | | | | | | | | | | | Previously, we translated into NIR and did all the optimizations and lowering as part of running fs_visitor. This meant that we did all of that work twice for fragment shaders - once for SIMD8, and again for SIMD16. We also had to redo it every time we hit a state based recompile. We now generate NIR once at link time. ARB programs don't have linking, so we instead generate it at ProgramStringNotify time. Mesa's fixed function vertex program handling doesn't bother to inform the driver about new programs at all (which is rather mean), so we generate NIR at the last minute, if it hasn't happened already. shader-db runs ~9.4% faster on my i7-5600U, with a release build. v2: Check NirOptions != NULL in ProgramStringNotify(). Don't bother using _mesa_program_enum_to_shader_stage as we already know it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Store num_direct_uniforms in the nir_shader.Kenneth Graunke2015-04-112-2/+6
| | | | | | | | | | | | | | Storing this here is pretty sketchy - I don't know if any driver other than i965 will want to use it. But this will make it a lot easier to generate NIR code at link time. We'll probably rework it anyway. (Ian suggested making nir_assign_var_locations_scalar_direct_first simply modify the nir_shader's fields, rather than passing pointers to them. If this stays long term, we should do that. But Jason and I suspect we'll be reworking this area again in the near future.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Move lower_output_reads to brw_link_shader().Kenneth Graunke2015-04-112-1/+3
| | | | | | | | This makes it so emit_nir_code() doesn't modify the GLSL IR. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Mark path as unreachable.Matt Turner2015-04-111-1/+1
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* i965: Remove useless null check.Matt Turner2015-04-111-4/+0
| | | | If it were null, we'd have just derefernced it two lines above.
* i965/fs/nir: Mark fallthrough.Matt Turner2015-04-111-0/+2
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* i965: Remove useless reg_offset >= 0 tests.Matt Turner2015-04-112-2/+0
| | | | Commit eb9bd3a1 changed the type of this field to uint16_t.
* freedreno/ir3/nir: couple little fixesRob Clark2015-04-111-2/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: handle system valuesRob Clark2015-04-111-3/+50
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: handle txs and query_levels tex opsRob Clark2015-04-111-4/+81
| | | | | | | | These correspond to the tgsi TXQ opcode (plus sneak in a fix for two-sided color) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: split out tex helpersRob Clark2015-04-111-34/+72
| | | | | | We'll need these in one or two other spots. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: simplify emit_tex()Rob Clark2015-04-112-61/+66
| | | | | | | | Just build up arrays for src0/src1, and use create_collect().. Also add back missing .3d flag for 3d/cube textures. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cp: handle indirect properlyRob Clark2015-04-111-13/+20
| | | | | | | | | I noticed some cases where we where trying to copy-propagate indirect src's into places they cannot go, like 2nd src for cat3 (mad, etc). Expand out valid_flags() to be aware of relativ flag, and fix up a few related spots. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: avoid getting stuck on addr conflictsRob Clark2015-04-111-32/+42
| | | | | | | | | | | | | | | | | | When we get in a scenario where we cannot schedule any more instructions due to address register conflict, clone the instruction that writes the address register, and switch the remaining unscheduled users for the current address register over to the new clone. This is simpler and more robust than the previous attempt (which tried and sometimes failed to ensure all other dependencies of users of the address register were scheduled first).. hint it would try to schedule instructions that were not actually needed for any output value. We probably need to do the same with predicate register, although so far it isn't so heavily used so we aren't running into problems with it (yet). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: add variable-indexing supportRob Clark2015-04-111-16/+204
| | | | | | | | A bit fugly.. try and make this cleaner.. note if we hoist all the get_addr() out of the loop we can drop the hashtable and just use create_addr().. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/asm: change assert to warningRob Clark2015-04-111-1/+4
| | | | | | | | It probably *should* be an assert, but for now TGSI f/e isn't very good about dealing w/ CONST vs ABS/NEG. So for debug builds, print a warning instead of crashing with an assert for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: set first_driver_paramRob Clark2015-04-111-0/+2
| | | | | | | Without this, a3xx breaks.. a4xx would too if it had already implemented support for passing driver params. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cp: support to swap mad src'sRob Clark2015-04-114-9/+43
| | | | | | | | | | | | | | | | For a normal MAD (ie. not MADSH), if first source is gpr and second source is const, we can swap the first two sources to avoid needing a mov instruction. This gives back the biggest advantage TGSI f/e had over NIR f/e for common shaders, since TGSI f/e had this logic in the f/e. Note that doing this in copy-prop step has the advantage that it will also work for cases like: MOV TEMP[b], CONST[x] MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c] Signed-off-by: Rob Clark <[email protected]>
* nir: fix bit of cargo-culting in lower_idivRob Clark2015-04-111-2/+0
| | | | | | | | | | | | I guess I was looking too much at how lower_system_values worked when writing lower_idiv. Since ttn wasn't emitting load_var for sysvals and the only drivers using lower_idiv were using ttn, I think nothing was broken as a result. But might as well fix this before it becomes a problem. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: split out lower_sub from lower_negateRob Clark2015-04-113-2/+5
| | | | | | | | | | Originally you had to have one or the other. But actually I don't want either. (Or rather I want whatever is the minimum # of instructions.) TODO: not sure where the best place to insert a check that driver hasn't set *both* lower_negate and lower_sub? Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: add support for system valuesRob Clark2015-04-111-0/+34
| | | | | | | | So far just the system values that freedreno supports, so we may add more later. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: fix TXDRob Clark2015-04-111-3/+17
| | | | | | | With TXD we also have the ddx/ddy sources (before the sampler). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add TXQ support (v2)Rob Clark2015-04-111-8/+51
| | | | | | | | | | Split out from ttn_tex() since it is kind of a weird instruction that maps to two NIR opcodes, and it was cleaner this way. v2: query_levels doesn't take any args Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: split out helper to get texture infoRob Clark2015-04-111-53/+59
| | | | | | | | We'll need this as well for TXQ. Split this out first to reduce noise in the next patch. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add support for temp arraysRob Clark2015-04-111-15/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the rest of NIR really would rather have these as variables rather than registers, create a nir_variable per array. But rather than completely re-arrange ttn to be variable based rather than register based, keep the registers. In the cases where there is a matching var for the reg, ttn_emit_instruction will append the appropriate intrinsic to get things back from the shadow reg into the variable. NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give an array id. But those just kinda suck, and should really go away. AFAICT we don't get those from glsl. Might be an issue for some other state tracker. v2: rework to use load_var/store_var with deref chains v3: create new "burner" reg for temporarily holding the (potentially writemask'd) dest after each instruction; add load_var to initialize temporary dest in case not all components are overwritten v4: review comments: asserts and use ttn_src_for_indirect() in ttn_array_deref() so we can drop later patch converting to use vec1 for addr reg (since ttn_src_for_indirect() handles the imov to vec1 from tgsi addr component that we want) v5: rebase: new requirements about parent mem ctx for derefs Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: minor cleanupRob Clark2015-04-111-5/+6
| | | | | | | Extract tgsi_dst->Index into a local.. split out from 'gallium/ttn: add support for temp arrays' for noise reduction.. Signed-off-by: Rob Clark <[email protected]>
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