summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* i965/fs: Fix ir_txs in emit_texture_gen4_simd16().Kenneth Graunke2015-06-261-3/+4
| | | | | | | | | | | We were not emitting the LOD, which led to message lengths of 1 instead of 3. Setting has_lod makes us emit the LOD, but I had to make changes to avoid emitting the non-existent coordinate as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91022 Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nv50/ir: propagate modifier to right arg when const-folding madIlia Mirkin2015-06-261-1/+4
| | | | | | | | | | An immediate has to be the second arg of an ADD operation. However we were mistakenly propagating the modifier of the non-folded value to the folded immediate argument. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91117 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* egl_dri2: Remove trailing whitespacesBoyan Ding2015-06-264-13/+13
| | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/skl: Fix aligning mt->total_width to the block sizeNeil Roberts2015-06-261-3/+2
| | | | | | | | | | | | | | | | | | | | brw_miptree_layout_2d tries to ensure that mt->total_width is a multiple of the compressed block size, presumably because it wouldn't be possible to make an image that has a fraction of a block. However it was doing this by aligning mt->total_width to align_w. Previously align_w has been used as a shortcut for getting the block width because before Gen9 the block width was always equal to the alignment. Commit 4ab8d59a2 tried to fix these cases to use the block width instead of the alignment but it missed this case. I think in practice this probably won't make any difference because the buffer for the texture will be allocated to be large enough to contain the entire pitch and libdrm aligns the pitch to the tile width anyway. However I think the patch is worth having to make the intention clearer. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Enable subdir-objects globally.Matt Turner2015-06-2618-34/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* mesa: fold duplicated GL/GL_CORE/GLES3 entry in get_hash_params.pyEmil Velikov2015-06-261-5/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ilo: define ILO_IMAGE_MAX_LEVEL_COUNTChia-I Wu2015-06-264-8/+16
| | | | | Define ILO_IMAGE_MAX_LEVEL_COUNT for ilo_image and remove unnecessary header includes.
* ilo: replace pipe_format by gen_surface_formatChia-I Wu2015-06-2613-142/+174
| | | | | Replace pipe_format by gen_surface_format in ilo_image. Change how depth format is specified in ilo_state_zs.
* ilo: always use the specified image formatChia-I Wu2015-06-264-69/+115
| | | | | Move silent promotion of PIPE_FORMAT_ETC1_RGB8 or combined depth/stencil out of core.
* ilo: replace pipe_texture_target by gen_surface_typeChia-I Wu2015-06-268-125/+98
| | | | | Replace pipe_texture_target by gen_surface_type in ilo_image. Change how GEN6_SURFTYPE_CUBE is specified in ilo_state_surface and ilo_state_zs.
* ilo: initialize ilo_image from ilo_image_infoChia-I Wu2015-06-263-179/+242
| | | | Convert pipe_resource to ilo_image_info for image initialization.
* ilo: remove ilo_image_disable_aux()Chia-I Wu2015-06-263-28/+2
| | | | Fail resource creation when aux bo allocation fails.
* ilo: improve SURFTYPE_BUFFER validationsChia-I Wu2015-06-262-81/+139
| | | | Reorganize the validations to make them more systematic.
* ilo: remove ilo_bufferChia-I Wu2015-06-2610-68/+109
| | | | | | | | | | Since the addition of ilo_vma, it was used only to pad a bo for sampling engine surfaces. Replace it entirely with these functions ilo_state_surface_buffer_size() ilo_state_vertex_buffer_size() ilo_state_index_buffer_size() ilo_state_sol_buffer_size()
* ilo: introduce ilo_vmaChia-I Wu2015-06-2621-315/+419
| | | | | This cleans up the code a bit and makes ilo_state_vector_resource_renamed() simpler and more robust. It also allows a single bo to back mulitple VMAs.
* mesa: remove unnecessary checks in _mesa_readpixels_needs_slow_pathIago Toral Quiroga2015-06-261-16/+0
| | | | | | | | | | | | | | | | readpixels_can_use_memcpy will later call _mesa_format_matches_format_and_type which does much tighter checks than these to decide if we can use memcpy for readpixels. Also, the checks do not seem to be extensive enough anyway, since we are checking for signed/unsigned conversion only when the framebuffer has integers, but the same checks could be done for other types anyway, since as long as there is a signed/unsigned conversion we can't memcpy. No regressions observed on i965/llvmpipe. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-251-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. In b2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea, we made this same change in the FS backend to great effect. Might as well keep it consistent and make the same change for vec4. Also, this took the time to run the test: ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1 from 6:49.62 to 3:31.40 on Timothy Arceri's machine. Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Use more compact hiz dimensionsBen Widawsky2015-06-251-15/+17
| | | | | | | | | | | | | gen8 had some special restrictions which don't seem to carry over to gen9. Quoting the spec for SKL: "The Z_Height and Z_Width values must equal those present in 3DSTATE_DEPTH_BUFFER incremented by one." This fixes nothing in piglit (and regresses nothing). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* radeonsi: don't fail in si_shader_io_get_unique_indexMarek Olšák2015-06-251-2/+6
| | | | Trivial. Picked from my tessellation branch.
* i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.Kenneth Graunke2015-06-251-5/+2
| | | | | | | | | This is always 0 - only brw_workaround_depthstencil_alignment ever sets it, and that doesn't run on Gen6+. My initial Broadwell depth state commit had this mistake. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* nir: Recognize max(min(a, 1.0), 0.0) as fsat(a).Kenneth Graunke2015-06-251-0/+1
| | | | | | | | | | | | | | We already recognize min(max(a, 0.0), 1.0) as a saturate, but neglected this variant (which is also handled by the GLSL IR pass). shader-db results on Broadwell: total instructions in shared programs: 7363046 -> 7362788 (-0.00%) instructions in affected programs: 11928 -> 11670 (-2.16%) helped: 64 HURT: 0 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* softpipe,llvmpipe: fix PIPE_SHADER_CAP_MAX_INPUTS valueMarek Olšák2015-06-252-2/+2
| | | | | | | | | | PIPE_MAX_SHADER_INPUTS was recently bumped to 80 because of tessellation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91099 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91101 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-245-0/+22
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED valueIan Romanick2015-06-241-0/+23
| | | | | | | | | | | | | | | | | | Commit b765119c changed the default value of all the counter bits to 64. However, older hardware only has 32 counter bits. This has only been build-tested. We don't have any tests that verify the advertised value against implementation behavior, so I don't know what additional testing could be done. NOTE: It appears that many Gallium drivers (at least r300 and i915g) have the same problem, but I don't see a way for the state-tracker to determine the counter size. Marek says, "For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed." Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: Alex Deucher <[email protected]>
* i965/fs_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-241-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. On my HSW desktop, one particular shadertoy test gets a 20% improvement in compile times: N Min Max Median Avg Stddev x 10 15.965 16.884 16.026 16.1822 0.34736846 + 10 12.813 13.052 12.876 12.8891 0.06913666 Difference at 95.0% confidence -3.2931 +/- 0.235316 -20.3501% +/- 1.45417% (Student's t, pooled s = 0.250444) Reviewed-by: Matt Turner <[email protected]>
* i965: Delete linked GLSL IR when using NIR.Tapani Pälli2015-06-241-1/+4
| | | | | | | | | | | This is based on Kenneth's patch to delete 'most of the IR'. Due to linker changes to clone variables, we can now free all of IR. Saves 58MB of memory when replaying a Dota 2 trace on Broadwell. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* glsl: clone inputs and outputs during linkingTapani Pälli2015-06-241-1/+3
| | | | | | | | | | | This increases memory pressure during linking but makes it easier for backend to free IR after it is not needed anymore. v2: use resource list as ralloc context in case of relink (Kenneth) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-2427-55/+55
| | | | | Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-245-314/+343
| | | | | | | | | Start trimming the fat from intel_batchbuffer.c. First by moving the set of routines for emitting PIPE_CONTROLS (along with the lore concerning hardware workarounds) to a separate brw_pipe_control.c Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Use a switch statement for detecting move-like operations.Kenneth Graunke2015-06-241-6/+14
| | | | | | | Suggested by Jason Ekstrand. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* svga: silence warnings about unexpected shader typeBrian Paul2015-06-241-1/+3
| | | | Trivial.
* st/mesa: remove unneeded pipe_surface_release() in st_render_texture()Brian Paul2015-06-241-2/+0
| | | | | | | | | | | | | | This caused us to always free the pipe_surface for the renderbuffer. The subsequent call to st_update_renderbuffer_surface() would typically just recreate it. Remove the call to pipe_surface_release() and let st_update_renderbuffer_surface() take care of freeing the old surface if it needs to be replaced (because of change to mipmap level, etc). This can save quite a few calls to pipe_context::create_surface() and surface_destroy(). Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/wgl: add stw_nopfuncs.h to the sources listsEmil Velikov2015-06-241-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* loader: move loader_open_device out of HAVE_LIBUDEV blockJulien Isorce2015-06-241-18/+18
| | | | | | | | | | | | | | | | | | Fixes the following build issue, when building without libudev. CCLD libGL.la ./.libs/libglx.a(dri2_glx.o): In function `dri2CreateScreen': src/glx/dri2_glx.c:1186: undefined reference to `loader_open_device' collect2: ld returned 1 exit status CCLD libEGL.la Undefined symbols for architecture x86_64: "_loader_open_device", referenced from: _dri2_initialize_x11_dri2 in libegl_dri2.a(platform_x11.o) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91077 Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/radeon: reduce BO cache timeoutGrigori Goronzy2015-06-241-1/+1
| | | | | | | | | | | | 1000 ms is an extreme value for typical interactive loads. A large cache has some disadvantages. Search for reusable BOs can take a long time and memory might get exhausted. Let's be rather conservative and use half of the old value, 500ms. This is beneficial to some loads on my test system and there are no regressions. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: align BO size to page sizeGrigori Goronzy2015-06-241-0/+6
| | | | | | | | | | | | This is the basic granularity for BO allocations. The alignment also helps with BO reuse by the cached bufmgr. This results in a huge 45% speedup in Metro 2033 Redux on my test system. The game relies on buffer orphaning with very small buffers (hundreds of bytes in size) and that did not work efficiently before. This change may also affect other applications and games. Reviewed-by: Marek Olšák <[email protected]>
* glsl: remove cross validation of interpolation qualifier with GLSL 4.40Tapani Pälli2015-06-241-1/+11
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Fix whitespace error in gen8_depth_state.cKenneth Graunke2015-06-231-1/+1
| | | | Trivial.
* i965: Don't count NIR instructions for shader-db.Kenneth Graunke2015-06-231-31/+0
| | | | | | | Matt, Jason, and I haven't found this useful in a long time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* winsys/radeon: Unmap GPU VM address range when destroying BOMichel Dänzer2015-06-243-4/+29
| | | | | | | | | | | | | | But only when doing so is safe according to the RADEON_INFO_VA_UNMAP_WORKING kernel query. This avoids kernel GPU VM address range conflicts when the BO has other references than the GEM handle being closed, e.g. when the BO is shared. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90537 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90873 Cc: "10.5 10.6" <[email protected]> Reviewed-by: Christian König <[email protected]>
* vc4: Also dump VC4_PACKET_LOAD_TILE_BUFFER_GENERAL.Eric Anholt2015-06-231-2/+14
|
* vc4: Add dumping for VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER.Eric Anholt2015-06-232-2/+38
|
* vc4: Don't try to CSE color reads.Eric Anholt2015-06-231-1/+2
| | | | | | It returns a new value for each sample in the TLB. We've already avoided trying to get the same index's color multiple times at the vc4_program.c level, so we're not losing anything by doing this.
* vc4: Make a helper for TLB color writes, too.Eric Anholt2015-06-232-1/+2
| | | | We've done so for all the other QIR instruction generation in this file.
* vc4: Pull the blending operation out to a separate function.Eric Anholt2015-06-231-38/+50
| | | | | It's fairly separate from the rest of the TLB operations at frag end time, and we'll need to run it multiple times to support MSAA blending.
* vc4: Clarify size calculation for Z/S writes.Eric Anholt2015-06-231-1/+1
| | | | | It's the same value for loads and stores, because they're basically the same packet.
* vc4: Add an "args" temporary for RCL setup.Eric Anholt2015-06-231-24/+24
|
* vc4: Reuse (and extend) the packet.h sizes for dumping.Eric Anholt2015-06-232-51/+58
|
* vc4: Fix printfs for blit fallbacks.Eric Anholt2015-06-231-3/+3
|
* tgsi_to_nir: Fix translation of TXF on MSAA targets.Eric Anholt2015-06-231-2/+10
| | | | | | Noticed while trying to add GL_ARB_texture_multisample support to vc4. Reviewed-by: Ilia Mirkin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 03:50:10 +0000