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* ra: Don't use regs as the ralloc context.Matt Turner2014-12-011-1/+1
| | | | | | | | | | The i965 backends pass something out of 'screen', which is allocated per-process, making using this as a ralloc context not thread-safe. All callers ra_alloc_interference_graph() already ralloc_free() its return value. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Initialize INTEL_DEBUG once per process.Matt Turner2014-12-011-1/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Initialize compaction tables once per process.Matt Turner2014-12-011-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Initialize static temporaries_allocate_names once per process.Matt Turner2014-12-011-1/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* util/u_atomic: Fix the unlocked implementation.José Fonseca2014-12-011-6/+6
| | | | | | | | | | | | | | | | | | It was totally broken: - p_atomic_dec_zero() was returning the negation of the expected value - p_atomic_inc_return()/p_atomic_dec_return() was post-incrementing/decrementing, hence returning the old value instead of the new - p_atomic_cmpxchg() was returning the new value on success, instead of the old It is clear this never used in the past. I wonder if it wouldn't be better to yank it altogether. Reviewed-by: Matt Turner <[email protected]>
* util/u_atomic: Add a simple test.José Fonseca2014-12-012-0/+146
| | | | | | | | | | | | | It was much easier for me to verify things build and run as expected with this simple test, than building and testing whole Mesa. With scons the test can be build and run merely by doing: scons u_atomic_test Building the test with autotools is left as a future exercise. Reviewed-by: Matt Turner <[email protected]>
* util: Make u_atomic.h typeless.Matt Turner2014-12-011-113/+93
| | | | | | | | | | | | like how C11's stdatomic.h provides generic functions. GCC's __sync_* builtins already take a variety of types, so that's simple. MSVC and Sun Studio don't, but we can implement it with something that looks a little crazy but is actually quite readable. Thanks to Jose for some MSVC fixes! Reviewed-by: Jose Fonseca <[email protected]>
* util: Use stdbool.h's bool rather than "boolean".Matt Turner2014-12-011-3/+5
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's GCC inline assembly.Matt Turner2014-12-011-122/+0
| | | | | | | GCC >= 4.1 support the __sync_* intrinsics. That seems like a sufficiently old baseline. Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's MSVC inline assembly.Matt Turner2014-12-011-70/+0
| | | | | | | There was already an intrinsics path that implemented all of the same functions, plus more. Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's Gallium dependence.Matt Turner2014-12-011-9/+6
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: s/INLINE/inline/ in u_atomic.h.Matt Turner2014-12-011-29/+29
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: Move u_atomic.h to src/util.Matt Turner2014-12-012-0/+2
| | | | | | To be shared outside of Gallium. Reviewed-by: Jose Fonseca <[email protected]>
* vc4: Introduce scheduling of QPU instructions.Eric Anholt2014-12-016-126/+722
| | | | | | | | | | | | This doesn't reschedule much currently, just tries to fit things into the regfile A/B write-versus-read slots (the cause of the improvements in shader-db), and hide texture fetch latency by scheduling setup early and results collection late (haven't performance tested it). This infrastructure will be important for doing instruction pairing, though. shader-db2 results: total instructions in shared programs: 61874 -> 59583 (-3.70%) instructions in affected programs: 50677 -> 48386 (-4.52%)
* vc4: Drop the explicit scoreboard wait.Eric Anholt2014-12-011-12/+11
| | | | This is actually implicitly handled by the TLB operations.
* vc4: Also deal with VPM reads at thread end.Eric Anholt2014-12-011-2/+6
| | | | | Prevents a regression with QPU scheduling, which happens to put the no-op reads for unused VPM contents end up at the end of the program.
* vc4: Fix assertion about SFU versus texturing.Eric Anholt2014-12-011-3/+4
| | | | | | | We're supposed to be checking that nothing else writes r4, which is done by the TMU result collection signal, not the coordinate setup. Avoids a regression when QPU instruction scheduling is introduced.
* vc4: Add another check for invalid TLB scoreboard handling.Eric Anholt2014-12-013-8/+39
| | | | This was caught by an assertion in the simulator.
* freedreno/a4xx: invalidate cache when vbo's changeRob Clark2014-12-011-0/+7
| | | | | | | | | Otherwise vertex shader can see stale cache data. This in particular happens when the same vbo is updated and reused. Not sure yet if vbo's at differing addresses but bound to same vertex buffer slot could have issues, but seems safest to flush whenever new vertex buffers are bound. Signed-off-by: Rob Clark <[email protected]>
* st/mesa: avoid exposing EXT_texture_integer for pre-GLSL 1.30Ilia Mirkin2014-11-301-0/+3
| | | | | | | | | For drivers building up to GL(ES)3, only expose the actual extension if the API will let it be used (e.g. via overrides/debug flags that enable higher versions). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: add missing integer formats and enable renderingIlia Mirkin2014-11-301-3/+30
| | | | | | | | The mesa state tracker doesn't fall back on similar integer formats, so they must all be provided. Remove the restriction against integer color rendering. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: enable sampling from integer texturesIlia Mirkin2014-11-305-5/+55
| | | | | | | | We need to produce a u32 destination type on integer sampling instructions, so keep that in a shader key set based on the currently-bound textures. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: allow each generation to hook into sampler view settingIlia Mirkin2014-11-305-3/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: don't use half precision shaders for int/float32Ilia Mirkin2014-11-303-10/+35
| | | | | | | Integer outputs end up getting mangled due to cov.f32f16, and float32 loses precision. Use full precision shaders in both of those cases. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: disable blending for integer formatsIlia Mirkin2014-11-302-2/+14
| | | | | | | Also add support for the BLENDABLE bind flag, similarly predicated on non-int formats. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: remove blend clamp enables from gmem/clearsIlia Mirkin2014-11-302-4/+2
| | | | | | | Just pass the data through unmolested. This probably has no effect since blending isn't actually enabled. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add format to emit info, use to set sint/uint flagsIlia Mirkin2014-11-303-2/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add 16-bit unorm/snorm texture formatsIlia Mirkin2014-11-301-6/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: remove unused arg parameterIlia Mirkin2014-11-301-7/+7
| | | | | | Leaving it around in the struct in case we want to use it later. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: fix UMADIlia Mirkin2014-11-301-9/+9
| | | | | | | | Looks like none of the mad variants do u16 * u16 + u32, so just add in the extra value "by hand". Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3 10.4" <[email protected]>
* freedreno/a4xx: stencil fixesRob Clark2014-11-308-10/+38
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-11-305-14/+24
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add render target format to fd4_emitRob Clark2014-11-305-42/+30
| | | | | | This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: unify vertex/texture formats into a single tableIlia Mirkin2014-11-292-351/+222
| | | | | | | | | | | | The table contains all the relevant information about each format. The helper functions now just do lookups in the table. Note that this adds support for a lot of formats that were previously unsupported. Additionally it adds disabled support for integer render buffers, which will require more work to actually enable. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: rename vertex/texture format enums to be more consistentIlia Mirkin2014-11-292-172/+177
| | | | | | | | Switch both of them from independently inconsistent conventions to having UINT/SINT/UNORM/SNORM/FLOAT/FIXED suffixes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: fd3_util -> fd3_formatIlia Mirkin2014-11-2915-22/+18
| | | | | | | All the "util" helpers are actually format-related Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: only enable blend clamp for non-float formatsIlia Mirkin2014-11-292-4/+7
| | | | | | | | This fixes arb_color_buffer_float-render GL_RGBA16F. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3 10.4" <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* i965: Add _CACHE_ in brw_cache_id enum names.Kenneth Graunke2014-11-2910-43/+43
| | | | | | | | | | | | BRW_CACHE_VS_PROG is more easily associated with program caches than plain BRW_VS_PROG. While we're at it, rename BRW_WM_PROG to BRW_CACHE_FS_PROG, to move away from the outdated Windowizer/Masker name. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.Kenneth Graunke2014-11-296-11/+12
| | | | | | | | | | | | | | | | | | | This flag signifies that we've emitted a new SAMPLER_STATE table. Given that we haven't cached those in years, CACHE_NEW_SAMPLER isn't a great name. Putting it in the BRW_NEW_* hierarchy would make more sense; BRW_NEW_SAMPLER_STATE_TABLE better reflects its actual purpose. When this flag is raised, the pointer to the SAMPLER_STATE table has changed, so we need to re-issue any packets which point to it (unit state on Gen4-5, 3DSTATE_SAMPLER_STATE_POINTERS on Gen6, and the per-stage variants on Gen7+). Saves 2 * sizeof(void *) bytes per context, as we remove useless aux_compare/aux_free function pointers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move some /* CACHE_NEW_SAMPLER */ comments.Kenneth Graunke2014-11-292-3/+2
| | | | | | | | | | | | | | | | | | | | | | Marking brw_stage_state::sampler_count as CACHE_NEW_SAMPLER is wrong. The number of samplers used by each program is actually computed at draw time (brw_try_draw_prims), based purely on the currently bound shader programs (gl_program::SamplersUsed). CACHE_NEW_SAMPLER means that we've emitted a new SAMPLER_STATE table. Although this could indicate that the number of samplers has changed, it could also simply mean that the contents of the table has changed (i.e. we've bound different textures). The real reason these atoms depend on CACHE_NEW_SAMPLER is because they include a pointer to the SAMPLER_STATE table. This was not commented. So, move the comments to the appropriate place. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.Kenneth Graunke2014-11-295-21/+23
| | | | | | | | | | | | We've been streaming these out for ages, so they basically have nothing to do with brw_state_cache.c. Saves 6 * sizeof(void *) bytes per context, as we won't have useless aux_compare/aux_free functions for them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.Kenneth Graunke2014-11-294-23/+8
| | | | | | | | | These always happen together; the extra atom just means another item to iterate through, flags to check, and a call through a function pointer. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.Kenneth Graunke2014-11-299-31/+11
| | | | | | | | | | | | | | | | | | | | | On Gen4-5, unit state is specified as indirect state, rather than commands. If any unit state changes, we upload it via brw_state_batch and arrange for 3DSTATE_PIPELINED_POINTERS to be re-emitted, which updates pointers to all unit state at once. Since there's only one command and state atom (brw_psp_urb_cs) that needs to know about this, there's no benefit to having six separate flags. We can combine CACHE_NEW_*_UNIT into a single flag. We also haven't cached these in a long time, so it doesn't make sense to use the "CACHE_NEW_" prefix. Instead, use the "BRW_NEW_" prefix. This also saves 12 * sizeof(void *) bytes of memory per context, as we remove useless aux_compare/aux_free functions for each CACHE bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Alphabetize brw_tracked_state flags and use a consistent style.Kenneth Graunke2014-11-2952-283/+359
| | | | | | | | | | | | | | | | Most of the dirty flags were listed in some arbitrary order. Some used bonus parenthesis. Some put multiple flags on one line, others put one per line. Some used tabs instead of spaces...but only on some lines. This patch settles on one flag per line, in alphabetical order, using spaces instead of tabs, and sheds the unnecessary parentheses. Sorting was mostly done with vim's visual block feature and !sort, although I alphabetized short lists by hand; it was pretty manual. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nv50/ir/tgsi: handle TGSI_OPCODE_ARRChristoph Bumiller2014-11-281-1/+4
| | | | | | | This instruction is used by st/nine. Reviewed-by: Ilia Mirkin <[email protected]> Cc: "10.4" <[email protected]>
* i965: Set prog_data->uses_kill if simulating alpha test via discards.Kenneth Graunke2014-11-273-3/+6
| | | | | | | | | | | | | | When using MRT on Gen4-5, we have to simulate GL's alpha test feature by emitting discards in the fragment shader. In this case, it makes sense to set prog_data->uses_kill, which means the fragment shader may kill pixels via the discard mechanism. This saves us from having to look an extra key value in a couple of places, including in the generator. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Use brw_wm_prog_data::uses_kill, not gl_fragment_program::UsesKillKenneth Graunke2014-11-275-6/+7
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Pass key->render_to_fbo via src1 of FS_OPCODE_DDY_*.Kenneth Graunke2014-11-273-11/+10
| | | | | | | | | This means the generator doesn't have to look at the key, which is a little nicer - we're pretty close to no key dependencies at all. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Handle derivative quality decisions in the front-end.Kenneth Graunke2014-11-275-52/+51
| | | | | | | | | | | | | | | | | | | | | Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Create prog_data temporary variables in PS state upload code.Kenneth Graunke2014-11-274-77/+81
| | | | | | | | | prog_data->foo is a bit more readable than brw->wm.prog_data->foo. The local variable definition is also a great location to put the obligatory /* CACHE_NEW_WM_PROG */ comment. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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