diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_context.h | 20 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 98 |
2 files changed, 118 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 48ebeb63ec2..c7627c15de3 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -272,6 +272,26 @@ struct iris_vtable { const struct pipe_draw_info *draw); void (*update_surface_base_address)(struct iris_batch *batch, struct iris_binder *binder); + void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg, + uint32_t val); + void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg, + uint64_t val); + void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset); + void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset); + void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset, + bool predicated); + void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset, + bool predicated); + void (*store_data_imm32)(struct iris_batch *batch, + struct iris_bo *bo, uint32_t offset, + uint32_t value); + void (*store_data_imm64)(struct iris_batch *batch, + struct iris_bo *bo, uint32_t offset, + uint64_t value); void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags, struct iris_bo *bo, uint32_t offset, uint64_t imm); diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 57b43876962..e2c8412dc1d 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4033,6 +4033,96 @@ iris_destroy_state(struct iris_context *ice) /* ------------------------------------------------------------------- */ +static void +iris_load_register_imm32(struct iris_batch *batch, uint32_t reg, + uint32_t val) +{ + _iris_emit_lri(batch, reg, val); +} + +static void +iris_load_register_imm64(struct iris_batch *batch, uint32_t reg, + uint64_t val) +{ + _iris_emit_lri(batch, reg + 0, val & 0xffffffff); + _iris_emit_lri(batch, reg + 4, val >> 32); +} + +/** + * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer. + */ +static void +iris_load_register_mem32(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset) +{ + iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { + lrm.RegisterAddress = reg; + lrm.MemoryAddress = ro_bo(bo, offset); + } +} + +/** + * Load a 64-bit value from a buffer into a MMIO register via + * two MI_LOAD_REGISTER_MEM commands. + */ +static void +iris_load_register_mem64(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset) +{ + iris_load_register_mem32(batch, reg + 0, bo, offset + 0); + iris_load_register_mem32(batch, reg + 4, bo, offset + 4); +} + +static void +iris_store_register_mem32(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset, + bool predicated) +{ + iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) { + srm.RegisterAddress = reg; + srm.MemoryAddress = rw_bo(bo, offset); + srm.PredicateEnable = predicated; + } +} + +static void +iris_store_register_mem64(struct iris_batch *batch, uint32_t reg, + struct iris_bo *bo, uint32_t offset, + bool predicated) +{ + iris_store_register_mem32(batch, reg + 0, bo, offset + 0, predicated); + iris_store_register_mem32(batch, reg + 4, bo, offset + 4, predicated); +} + +static void +iris_store_data_imm32(struct iris_batch *batch, + struct iris_bo *bo, uint32_t offset, + uint32_t imm) +{ + iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) { + sdi.Address = rw_bo(bo, offset); + sdi.ImmediateData = imm; + } +} + +static void +iris_store_data_imm64(struct iris_batch *batch, + struct iris_bo *bo, uint32_t offset, + uint64_t imm) +{ + /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of + * 2 in genxml but it's actually variable length and we need 5 DWords. + */ + void *map = iris_get_command_space(batch, 4 * 5); + _iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) { + sdi.DWordLength = 5 - 2; + sdi.Address = rw_bo(bo, offset); + sdi.ImmediateData = imm; + } +} + +/* ------------------------------------------------------------------- */ + static unsigned flags_to_post_sync_op(uint32_t flags) { @@ -4495,6 +4585,14 @@ genX(init_state)(struct iris_context *ice) ice->vtbl.upload_render_state = iris_upload_render_state; ice->vtbl.update_surface_base_address = iris_update_surface_base_address; ice->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control; + ice->vtbl.load_register_imm32 = iris_load_register_imm32; + ice->vtbl.load_register_imm64 = iris_load_register_imm64; + ice->vtbl.load_register_mem32 = iris_load_register_mem32; + ice->vtbl.load_register_mem64 = iris_load_register_mem64; + ice->vtbl.store_register_mem32 = iris_store_register_mem32; + ice->vtbl.store_register_mem64 = iris_store_register_mem64; + ice->vtbl.store_data_imm32 = iris_store_data_imm32; + ice->vtbl.store_data_imm64 = iris_store_data_imm64; ice->vtbl.derived_program_state_size = iris_derived_program_state_size; ice->vtbl.store_derived_program_state = iris_store_derived_program_state; ice->vtbl.create_so_decl_list = iris_create_so_decl_list; |