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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c18
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c2
2 files changed, 12 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 2f2c17cd05e..f79eae29c74 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -593,19 +593,21 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
templ.nr_samples = 1;
flags = rtex->surface.flags | RADEON_SURF_FMASK;
- /* Use the same parameters and tile mode. */
- fmask.bankw = rtex->surface.bankw;
- fmask.bankh = rtex->surface.bankh;
- fmask.mtilea = rtex->surface.mtilea;
- fmask.tile_split = rtex->surface.tile_split;
+ if (rscreen->chip_class <= CAYMAN) {
+ /* Use the same parameters and tile mode. */
+ fmask.bankw = rtex->surface.bankw;
+ fmask.bankh = rtex->surface.bankh;
+ fmask.mtilea = rtex->surface.mtilea;
+ fmask.tile_split = rtex->surface.tile_split;
+
+ if (nr_samples <= 4)
+ fmask.bankh = 4;
+ }
switch (nr_samples) {
case 2:
case 4:
bpe = 1;
- if (rscreen->chip_class <= CAYMAN) {
- fmask.bankh = 4;
- }
break;
case 8:
bpe = 4;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index ff71bcb8b9d..45edcc28734 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -436,6 +436,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
* for shared resources. This is for 2D tiling only. */
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
+ assert(!(flags & RADEON_SURF_FMASK));
+
/* If any of these parameters are incorrect, the calculation
* will fail. */
AddrTileInfoIn.banks = surf->num_banks;