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-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d6643ca4d72..86a2d53f29f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -468,6 +468,15 @@ intel_miptree_choose_tiling(struct brw_context *brw,
if (brw->gen < 6)
return I915_TILING_X;
+ /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
+ * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
+ * or Linear."
+ * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
+ * all the way back to 965, but is explicitly permitted on Gen7.
+ */
+ if (brw->gen != 7 && mt->cpp >= 16)
+ return I915_TILING_X;
+
return I915_TILING_Y | I915_TILING_X;
}