diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 15 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.h | 3 |
4 files changed, 21 insertions, 21 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index ad0d9770ec2..8a635e3ce4b 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -166,7 +166,7 @@ brw_fast_clear_depth(struct gl_context *ctx) mt->fast_clear_color.f32[0] = ctx->Depth.Clear; } - if (fb->MaxNumLayers > 0) { + if (depth_att->Layered) { intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, depth_irb->layer_count, BLORP_HIZ_OP_DEPTH_CLEAR); @@ -178,7 +178,15 @@ brw_fast_clear_depth(struct gl_context *ctx) /* Now, the HiZ buffer contains data that needs to be resolved to the depth * buffer. */ - intel_renderbuffer_att_set_needs_depth_resolve(depth_att); + if (depth_att->Layered) { + for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { + intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level, + depth_irb->mt_layer + layer); + } + } else { + intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level, + depth_irb->mt_layer); + } return true; } diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 23a3c6c5c8d..f7287318a5a 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -373,7 +373,17 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) if (back_irb) back_irb->need_downsample = true; if (depth_irb && brw_depth_writes_enabled(brw)) { - intel_renderbuffer_att_set_needs_depth_resolve(depth_att); + if (depth_att->Layered) { + for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { + intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt, + depth_irb->mt_level, + depth_irb->mt_layer + layer); + } + } else { + intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt, + depth_irb->mt_level, + depth_irb->mt_layer); + } brw_render_cache_set_add_bo(brw, depth_irb->mt->bo); } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index c3c919c24fa..864ff32a1bb 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -938,21 +938,6 @@ intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb) } void -intel_renderbuffer_att_set_needs_depth_resolve(struct gl_renderbuffer_attachment *att) -{ - struct intel_renderbuffer *irb = intel_renderbuffer(att->Renderbuffer); - if (irb->mt) { - if (att->Layered) { - intel_miptree_set_all_slices_need_depth_resolve(irb->mt, irb->mt_level); - } else { - intel_miptree_slice_set_needs_depth_resolve(irb->mt, - irb->mt_level, - irb->mt_layer); - } - } -} - -void intel_renderbuffer_move_to_temp(struct brw_context *brw, struct intel_renderbuffer *irb, bool invalidate) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h index 40c4f27a341..86811b4225e 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.h +++ b/src/mesa/drivers/dri/i965/intel_fbo.h @@ -195,9 +195,6 @@ intel_renderbuffer_get_tile_offsets(struct intel_renderbuffer *irb, bool intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb); -void -intel_renderbuffer_att_set_needs_depth_resolve(struct gl_renderbuffer_attachment *att); - void intel_renderbuffer_move_to_temp(struct brw_context *brw, struct intel_renderbuffer *irb, |