diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 33 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 33 | ||||
-rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 1 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/cik_sdma.c | 12 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_dma.c | 8 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 18 | ||||
-rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 6 |
7 files changed, 20 insertions, 91 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index eec567c7150..5224e420119 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -35,13 +35,12 @@ static inline unsigned evergreen_array_mode(unsigned mode) { switch (mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED; break; case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1; break; case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1; - default: - case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL; } } @@ -758,6 +757,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, non_disp_tiling = tmp->non_disp_tiling; switch (surflevel[base_level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; break; @@ -767,10 +767,6 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, case RADEON_SURF_MODE_1D: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; - case RADEON_SURF_MODE_LINEAR: - default: - array_mode = V_028C70_ARRAY_LINEAR_GENERAL; - break; } macro_aspect = tmp->surface.mtilea; bankw = tmp->surface.bankw; @@ -1006,14 +1002,8 @@ void evergreen_init_color_surface(struct r600_context *rctx, bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE; offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { - assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); - offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - color_view = 0; - } else - color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | - S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); + color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | + S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; @@ -1022,6 +1012,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, } color_info = 0; switch (rtex->surface.level[level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED); non_disp_tiling = 1; @@ -1034,11 +1025,6 @@ void evergreen_init_color_surface(struct r600_context *rctx, color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1); non_disp_tiling = rtex->non_disp_tiling; break; - case RADEON_SURF_MODE_LINEAR: - default: - color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL); - non_disp_tiling = 1; - break; } tile_split = rtex->surface.tile_split; macro_aspect = rtex->surface.mtilea; @@ -1201,7 +1187,6 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, break; case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_LINEAR_ALIGNED: - case RADEON_SURF_MODE_LINEAR: default: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; @@ -3391,9 +3376,6 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */ @@ -3406,7 +3388,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, pitch_tile_max = ((pitch / bpp) / 8) - 1; nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks); - if (dst_mode == RADEON_SURF_MODE_LINEAR) { + if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { /* T2L */ array_mode = evergreen_array_mode(src_mode); slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); @@ -3538,9 +3520,6 @@ static void evergreen_dma_copy(struct pipe_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { /* FIXME evergreen can do partial blit */ diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 75a43639053..22910962794 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -717,7 +717,9 @@ r600_create_sampler_view_custom(struct pipe_context *ctx, depth = texture->array_size; } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) depth = texture->array_size / 6; + switch (tmp->surface.level[offset_level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: array_mode = V_038000_ARRAY_LINEAR_ALIGNED; break; @@ -727,10 +729,6 @@ r600_create_sampler_view_custom(struct pipe_context *ctx, case RADEON_SURF_MODE_2D: array_mode = V_038000_ARRAY_2D_TILED_THIN1; break; - case RADEON_SURF_MODE_LINEAR: - default: - array_mode = V_038000_ARRAY_LINEAR_GENERAL; - break; } if (state->format == PIPE_FORMAT_X24S8_UINT || @@ -838,14 +836,8 @@ static void r600_init_color_surface(struct r600_context *rctx, } offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { - assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); - offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - color_view = 0; - } else - color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | - S_028080_SLICE_MAX(surf->base.u.tex.last_layer); + color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | + S_028080_SLICE_MAX(surf->base.u.tex.last_layer); pitch = rtex->surface.level[level].nblk_x / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; @@ -854,6 +846,7 @@ static void r600_init_color_surface(struct r600_context *rctx, } color_info = 0; switch (rtex->surface.level[level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); break; @@ -863,10 +856,6 @@ static void r600_init_color_surface(struct r600_context *rctx, case RADEON_SURF_MODE_2D: color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); break; - case RADEON_SURF_MODE_LINEAR: - default: - color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); - break; } desc = util_format_description(surf->base.format); @@ -1055,7 +1044,6 @@ static void r600_init_depth_surface(struct r600_context *rctx, break; case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_LINEAR_ALIGNED: - case RADEON_SURF_MODE_LINEAR: default: array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; break; @@ -2842,13 +2830,12 @@ void r600_update_db_shader_control(struct r600_context * rctx) static inline unsigned r600_array_mode(unsigned mode) { switch (mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED; break; case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1; break; case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1; - default: - case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL; } } @@ -2876,16 +2863,13 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); y = 0; lbpp = util_logbase2(bpp); pitch_tile_max = ((pitch / bpp) / 8) - 1; - if (dst_mode == RADEON_SURF_MODE_LINEAR) { + if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { /* T2L */ array_mode = r600_array_mode(src_mode); slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); @@ -3006,9 +2990,6 @@ static void r600_dma_copy(struct pipe_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { /* strict requirement on r6xx/r7xx */ diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 0df673457ea..1612c135520 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -326,7 +326,6 @@ enum radeon_feature_id { #define RADEON_SURF_TYPE_2D_ARRAY 5 #define RADEON_SURF_MODE_MASK 0xFF #define RADEON_SURF_MODE_SHIFT 8 -#define RADEON_SURF_MODE_LINEAR 0 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1 #define RADEON_SURF_MODE_1D 2 #define RADEON_SURF_MODE_2D 3 diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 6eb62dcc890..07a7d945301 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -126,17 +126,14 @@ static void cik_sdma_copy_tile(struct si_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); - assert(src_mode == RADEON_SURF_MODE_LINEAR || dst_mode == RADEON_SURF_MODE_LINEAR); + assert(src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED || dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED); sub_op = CIK_SDMA_COPY_SUB_OPCODE_TILED; lbpe = util_logbase2(bpe); pitch_tile_max = ((pitch / bpe) / 8) - 1; - detile = dst_mode == RADEON_SURF_MODE_LINEAR; + detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; rlinear = detile ? rdst : rsrc; rtiled = detile ? rsrc : rdst; linear_lvl = detile ? dst_level : src_level; @@ -276,12 +273,9 @@ void cik_sdma_copy(struct pipe_context *ctx, copy_height = src_box->height / rsrc->surface.blk_h; dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; /* Dimensions must be aligned to (macro)tiles */ - switch (src_mode == RADEON_SURF_MODE_LINEAR ? dst_mode : src_mode) { + switch (src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? dst_mode : src_mode) { case RADEON_SURF_MODE_1D: if ((src_x % 8) || (src_y % 8) || (dst_x % 8) || (dst_y % 8) || (copy_height % 8)) diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 0efca193951..688edbe601f 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -126,16 +126,13 @@ static void si_dma_copy_tile(struct si_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); sub_cmd = SI_DMA_COPY_TILED; lbpp = util_logbase2(bpp); pitch_tile_max = ((pitch / bpp) / 8) - 1; - detile = dst_mode == RADEON_SURF_MODE_LINEAR; + detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; rlinear = detile ? rdst : rsrc; rtiled = detile ? rsrc : rdst; linear_lvl = detile ? dst_level : src_level; @@ -270,9 +267,6 @@ void si_dma_copy(struct pipe_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w || src_box->width != src_w || diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index c214932e28b..1dd468b596d 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -58,15 +58,13 @@ void si_init_atom(struct si_context *sctx, struct r600_atom *atom, unsigned si_array_mode(unsigned mode) { switch (mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_009910_ARRAY_LINEAR_ALIGNED; case RADEON_SURF_MODE_1D: return V_009910_ARRAY_1D_TILED_THIN1; case RADEON_SURF_MODE_2D: return V_009910_ARRAY_2D_TILED_THIN1; - default: - case RADEON_SURF_MODE_LINEAR: - return V_009910_ARRAY_LINEAR_GENERAL; } } @@ -2119,17 +2117,8 @@ static void si_initialize_color_surface(struct si_context *sctx, int i; unsigned blend_clamp = 0, blend_bypass = 0; - /* Layered rendering doesn't work with LINEAR_GENERAL. - * (LINEAR_ALIGNED and others work) */ - if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { - assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); - offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - color_view = 0; - } else { - color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | - S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); - } + color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | + S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; @@ -2346,7 +2335,6 @@ static void si_init_depth_surface(struct si_context *sctx, break; case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_LINEAR_ALIGNED: - case RADEON_SURF_MODE_LINEAR: default: array_mode = V_02803C_ARRAY_1D_TILED_THIN1; break; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 1164a3058c5..5ee6be490ed 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -226,9 +226,6 @@ static int compute_level(struct amdgpu_winsys *ws, surf_level->nblk_z = 1; switch (AddrSurfInfoOut->tileMode) { - case ADDR_TM_LINEAR_GENERAL: - surf_level->mode = RADEON_SURF_MODE_LINEAR; - break; case ADDR_TM_LINEAR_ALIGNED: surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED; break; @@ -316,9 +313,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, /* Set the requested tiling mode. */ switch (mode) { - case RADEON_SURF_MODE_LINEAR: - AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_GENERAL; - break; case RADEON_SURF_MODE_LINEAR_ALIGNED: AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED; break; |