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-rw-r--r--src/amd/vulkan/radv_shader.h3
-rw-r--r--src/amd/vulkan/radv_shader_info.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b711cba80cf..679fa442798 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -159,6 +159,9 @@ struct radv_shader_info {
} vs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ } gs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;
struct {
bool force_persample;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index a436bd75343..b45b4c0c95b 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -134,6 +134,12 @@ gather_intrinsic_store_var_info(const nir_shader *nir,
instr->const_index[0] << comp;
}
break;
+ case MESA_SHADER_GEOMETRY:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->gs.output_usage_mask[idx + i + const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
case MESA_SHADER_TESS_EVAL:
for (unsigned i = 0; i < attrib_count; i++) {
info->tes.output_usage_mask[idx + i + const_offset] |=