diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_compact.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_dump.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c b/src/mesa/drivers/dri/i965/brw_eu_compact.c index 67f0b45ac04..b798931140f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_compact.c +++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c @@ -802,7 +802,7 @@ set_3src_control_index(const struct brw_device_info *devinfo, if (devinfo->gen >= 9 || devinfo->is_cherryview) uncompacted |= brw_inst_bits(src, 36, 35) << 24; /* 2b */ - for (int i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) { if (gen8_3src_control_index_table[i] == uncompacted) { brw_compact_inst_set_3src_control_index(dst, i); return true; @@ -836,7 +836,7 @@ set_3src_source_index(const struct brw_device_info *devinfo, (brw_inst_bits(src, 104, 104) << 44); /* 1b */ } - for (int i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) { if (gen8_3src_source_index_table[i] == uncompacted) { brw_compact_inst_set_3src_source_index(dst, i); return true; diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c index b6f4d598e1d..0c974c4c807 100644 --- a/src/mesa/drivers/dri/i965/brw_state_dump.c +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c @@ -376,13 +376,13 @@ dump_sdc(struct brw_context *brw, uint32_t offset) static void dump_sampler_state(struct brw_context *brw, uint32_t offset, uint32_t size) { - int i; + unsigned i; uint32_t *samp = brw->batch.bo->virtual + offset; for (i = 0; i < size / 16; i++) { char name[20]; - sprintf(name, "WM SAMP%d", i); + sprintf(name, "WM SAMP%u", i); batch_out(brw, name, offset, 0, "filtering\n"); batch_out(brw, name, offset, 1, "wrapping, lod\n"); batch_out(brw, name, offset, 2, "default color pointer\n"); diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b2ca9c2c0e7..01c090014e4 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -797,7 +797,7 @@ brw_pipeline_state_finished(struct brw_context *brw, enum brw_pipeline pipeline) { /* Save all dirty state into the other pipelines */ - for (int i = 0; i < BRW_NUM_PIPELINES; i++) { + for (unsigned i = 0; i < BRW_NUM_PIPELINES; i++) { if (i != pipeline) { brw->state.pipelines[i].mesa |= brw->NewGLState; brw->state.pipelines[i].brw |= brw->ctx.NewDriverState; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 19f66b70a59..1259664de2a 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1539,7 +1539,7 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, unsigned H_i = H0; unsigned Z_i = Z0; hz_height = 0; - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { unsigned h_i = ALIGN(H_i, vertical_align); /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */ hz_height += h_i * Z_i; @@ -1635,7 +1635,7 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, unsigned Z_i = Z0; unsigned sum_h_i = 0; unsigned hz_height_3d_sum = 0; - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { unsigned i = level - mt->first_level; unsigned h_i = ALIGN(H_i, vertical_align); /* sum(i=2 to m; h_i) */ @@ -1768,11 +1768,11 @@ intel_miptree_alloc_hiz(struct brw_context *brw, return false; /* Mark that all slices need a HiZ resolve. */ - for (int level = mt->first_level; level <= mt->last_level; ++level) { + for (unsigned level = mt->first_level; level <= mt->last_level; ++level) { if (!intel_miptree_level_enable_hiz(brw, mt, level)) continue; - for (int layer = 0; layer < mt->level[level].depth; ++layer) { + for (unsigned layer = 0; layer < mt->level[level].depth; ++layer) { struct intel_resolve_map *m = malloc(sizeof(struct intel_resolve_map)); exec_node_init(&m->link); m->level = level; |