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-rw-r--r--src/amd/vulkan/radv_shader.c27
1 files changed, 26 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index a86ba2a01c0..3688680107f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -245,8 +245,33 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_shader_gather_info(nir, entry_point->impl);
+ /* While it would be nice not to have this flag, we are constrained
+ * by the reality that LLVM 5.0 doesn't have working VGPR indexing
+ * on GFX9.
+ */
+ bool llvm_has_working_vgpr_indexing =
+ device->physical_device->rad_info.chip_class <= VI;
+
+ /* TODO: Indirect indexing of GS inputs is unimplemented.
+ *
+ * TCS and TES load inputs directly from LDS or offchip memory, so
+ * indirect indexing is trivial.
+ */
nir_variable_mode indirect_mask = 0;
- indirect_mask |= nir_var_shader_in;
+ if (nir->stage == MESA_SHADER_GEOMETRY ||
+ (nir->stage != MESA_SHADER_TESS_CTRL &&
+ nir->stage != MESA_SHADER_TESS_EVAL &&
+ !llvm_has_working_vgpr_indexing)) {
+ indirect_mask |= nir_var_shader_in;
+ }
+
+ /* TODO: We shouldn't need to do this, however LLVM isn't currently
+ * smart enough to handle indirects without causing excess spilling
+ * causing the gpu to hang.
+ *
+ * See the following thread for more details of the problem:
+ * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
+ */
indirect_mask |= nir_var_local;
nir_lower_indirect_derefs(nir, indirect_mask);