3 files changed, 18 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp
index 54c8511ae8d..f347d9f52ab 100644
--- a/src/intel/compiler/brw_eu.cpp
+++ b/src/intel/compiler/brw_eu.cpp
@@ -146,6 +146,12 @@ brw_get_default_access_mode(struct brw_codegen *p)
    return p->current->access_mode;
 }
 
+tgl_swsb
+brw_get_default_swsb(struct brw_codegen *p)
+{
+   return p->current->swsb;
+}
+
 void
 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 {
@@ -288,6 +294,11 @@ void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
    p->current->acc_wr_control = value;
 }
 
+void brw_set_default_swsb(struct brw_codegen *p, tgl_swsb value)
+{
+   p->current->swsb = value;
+}
+
 void brw_push_insn_state( struct brw_codegen *p )
 {
    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 654246d7fdd..c35725bfe2b 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -59,6 +59,9 @@ struct brw_insn_state {
    /* One of BRW_MASK_* */
    unsigned mask_control:1;
 
+   /* Scheduling info for Gen12+ */
+   struct tgl_swsb swsb;
+
    bool saturate:1;
 
    /* One of BRW_ALIGN_* */
@@ -139,6 +142,7 @@ void brw_push_insn_state( struct brw_codegen *p );
 unsigned brw_get_default_exec_size(struct brw_codegen *p);
 unsigned brw_get_default_group(struct brw_codegen *p);
 unsigned brw_get_default_access_mode(struct brw_codegen *p);
+struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
@@ -154,6 +158,7 @@ void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate
 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
+void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
 
 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
 		      void *mem_ctx);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e5d212bdba4..1b3b21213a9 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -616,6 +616,8 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
    brw_inst_set_compression(devinfo, insn, state->compressed);
    brw_inst_set_access_mode(devinfo, insn, state->access_mode);
    brw_inst_set_mask_control(devinfo, insn, state->mask_control);
+   if (devinfo->gen >= 12)
+      brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(state->swsb));
    brw_inst_set_saturate(devinfo, insn, state->saturate);
    brw_inst_set_pred_control(devinfo, insn, state->predicate);
    brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);