diff options
Diffstat (limited to 'src')
22 files changed, 190 insertions, 189 deletions
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 3c963c60eaf..ae3e3c50930 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2109,7 +2109,7 @@ shrink_surface_params(const struct isl_device *dev, x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa; y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa; isl_tiling_get_intratile_offset_sa(info->surf.tiling, - info->surf.format, info->surf.row_pitch, + info->surf.format, info->surf.row_pitch_B, x_offset_sa, y_offset_sa, &byte_offset, &info->tile_x_sa, &info->tile_y_sa); @@ -2709,7 +2709,7 @@ do_buffer_copy(struct blorp_batch *batch, .levels = 1, .array_len = 1, .samples = 1, - .row_pitch = width * block_size, + .row_pitch_B = width * block_size, .usage = ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_RENDER_TARGET_BIT, .tiling_flags = ISL_TILING_LINEAR_BIT); diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index b4c744020d9..5b575dccc22 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -1089,7 +1089,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, isl_surf_get_image_offset_el(surf->aux_surf, level, layer, z, &x_offset_el, &y_offset_el); isl_tiling_get_intratile_offset_el(surf->aux_surf->tiling, aux_fmtl->bpb, - surf->aux_surf->row_pitch, + surf->aux_surf->row_pitch_B, x_offset_el, y_offset_el, &offset_B, &x_offset_el, &y_offset_el); params.dst.addr.offset += offset_B; @@ -1178,7 +1178,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, .levels = 1, .array_len = 1, .samples = 1, - .row_pitch = surf->aux_surf->row_pitch, + .row_pitch_B = surf->aux_surf->row_pitch_B, .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT, .tiling_flags = ISL_TILING_Y0_BIT); assert(ok); diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index f39d8a79995..359293cfcb2 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1261,12 +1261,12 @@ static uint32_t isl_calc_linear_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *info, const struct isl_extent2d *phys_total_el, - uint32_t alignment) + uint32_t alignment_B) { const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); const uint32_t bs = fmtl->bpb / 8; - return isl_align_npot(bs * phys_total_el->w, alignment); + return isl_align_npot(bs * phys_total_el->w, alignment_B); } static uint32_t @@ -1274,7 +1274,7 @@ isl_calc_tiled_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, const struct isl_extent2d *phys_total_el, - uint32_t alignment) + uint32_t alignment_B) { const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); @@ -1285,7 +1285,7 @@ isl_calc_tiled_min_row_pitch(const struct isl_device *dev, isl_align_div(phys_total_el->w * tile_el_scale, tile_info->logical_extent_el.width); - assert(alignment == tile_info->phys_extent_B.width); + assert(alignment_B == tile_info->phys_extent_B.width); return total_w_tl * tile_info->phys_extent_B.width; } @@ -1294,14 +1294,14 @@ isl_calc_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, const struct isl_extent2d *phys_total_el, - uint32_t alignment) + uint32_t alignment_B) { if (tile_info->tiling == ISL_TILING_LINEAR) { return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el, - alignment); + alignment_B); } else { return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info, - phys_total_el, alignment); + phys_total_el, alignment_B); } } @@ -1327,15 +1327,15 @@ isl_calc_row_pitch(const struct isl_device *dev, const struct isl_tile_info *tile_info, enum isl_dim_layout dim_layout, const struct isl_extent2d *phys_total_el, - uint32_t *out_row_pitch) + uint32_t *out_row_pitch_B) { - uint32_t alignment = + uint32_t alignment_B = isl_calc_row_pitch_alignment(surf_info, tile_info); /* If pitch isn't given and it can be chosen freely, align it by cache line * allowing one to use blit engine on the surface. */ - if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) { + if (surf_info->row_pitch_B == 0 && tile_info->tiling == ISL_TILING_LINEAR) { /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress: * * "Base address of the destination surface: X=0, Y=0. Lower 32bits @@ -1343,28 +1343,28 @@ isl_calc_row_pitch(const struct isl_device *dev, * enabled), this address must be 4KB-aligned. When Tiling is not * enabled, this address should be CL (64byte) aligned." */ - alignment = MAX2(alignment, 64); + alignment_B = MAX2(alignment_B, 64); } - const uint32_t min_row_pitch = + const uint32_t min_row_pitch_B = isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el, - alignment); + alignment_B); - uint32_t row_pitch = min_row_pitch; + uint32_t row_pitch_B = min_row_pitch_B; - if (surf_info->row_pitch != 0) { - row_pitch = surf_info->row_pitch; + if (surf_info->row_pitch_B != 0) { + row_pitch_B = surf_info->row_pitch_B; - if (row_pitch < min_row_pitch) + if (row_pitch_B < min_row_pitch_B) return false; - if (row_pitch % alignment != 0) + if (row_pitch_B % alignment_B != 0) return false; } - const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width; + const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width; - if (row_pitch == 0) + if (row_pitch_B == 0) return false; if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { @@ -1375,20 +1375,20 @@ isl_calc_row_pitch(const struct isl_device *dev, if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_STORAGE_BIT)) && - !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT | ISL_SURF_USAGE_MCS_BIT)) && - !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) && - !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) && - !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) return false; const uint32_t stencil_pitch_bits = dev->use_separate_stencil ? @@ -1396,11 +1396,11 @@ isl_calc_row_pitch(const struct isl_device *dev, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info); if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) && - !pitch_in_range(row_pitch, stencil_pitch_bits)) + !pitch_in_range(row_pitch_B, stencil_pitch_bits)) return false; done: - *out_row_pitch = row_pitch; + *out_row_pitch_B = row_pitch_B; return true; } @@ -1456,15 +1456,15 @@ isl_surf_init_s(const struct isl_device *dev, array_pitch_span, &array_pitch_el_rows, &phys_total_el); - uint32_t row_pitch; + uint32_t row_pitch_B; if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout, - &phys_total_el, &row_pitch)) + &phys_total_el, &row_pitch_B)) return false; - uint32_t base_alignment; - uint64_t size; + uint32_t base_alignment_B; + uint64_t size_B; if (tiling == ISL_TILING_LINEAR) { - size = (uint64_t) row_pitch * phys_total_el.h; + size_B = (uint64_t) row_pitch_B * phys_total_el.h; /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress: * @@ -1475,25 +1475,25 @@ isl_surf_init_s(const struct isl_device *dev, * surfaces have no alignment requirements (byte alignment is * sufficient.)" */ - base_alignment = MAX(1, info->min_alignment); + base_alignment_B = MAX(1, info->min_alignment_B); if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { if (isl_format_is_yuv(info->format)) { - base_alignment = MAX(base_alignment, fmtl->bpb / 4); + base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 4); } else { - base_alignment = MAX(base_alignment, fmtl->bpb / 8); + base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 8); } } - base_alignment = isl_round_up_to_power_of_two(base_alignment); + base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B); } else { const uint32_t total_h_tl = isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height); - size = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch; + size_B = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch_B; - const uint32_t tile_size = tile_info.phys_extent_B.width * - tile_info.phys_extent_B.height; - assert(isl_is_pow2(info->min_alignment) && isl_is_pow2(tile_size)); - base_alignment = MAX(info->min_alignment, tile_size); + const uint32_t tile_size_B = tile_info.phys_extent_B.width * + tile_info.phys_extent_B.height; + assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B)); + base_alignment_B = MAX(info->min_alignment_B, tile_size_B); } if (ISL_DEV_GEN(dev) < 9) { @@ -1505,7 +1505,7 @@ isl_surf_init_s(const struct isl_device *dev, * * This comment is applicable to all Pre-gen9 platforms. */ - if (size > (uint64_t) 1 << 31) + if (size_B > (uint64_t) 1 << 31) return false; } else if (ISL_DEV_GEN(dev) < 11) { /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes: @@ -1514,11 +1514,11 @@ isl_surf_init_s(const struct isl_device *dev, * All pixels within the surface must be contained within 2^38 bytes * of the base address." */ - if (size > (uint64_t) 1 << 38) + if (size_B > (uint64_t) 1 << 38) return false; } else { /* gen11+ platforms raised this limit to 2^44 bytes. */ - if (size > (uint64_t) 1 << 44) + if (size_B > (uint64_t) 1 << 44) return false; } @@ -1536,9 +1536,9 @@ isl_surf_init_s(const struct isl_device *dev, .logical_level0_px = logical_level0_px, .phys_level0_sa = phys_level0_sa, - .size = size, - .alignment = base_alignment, - .row_pitch = row_pitch, + .size_B = size_B, + .alignment_B = base_alignment_B, + .row_pitch_B = row_pitch_B, .array_pitch_el_rows = array_pitch_el_rows, .array_pitch_span = array_pitch_span, @@ -1689,7 +1689,7 @@ bool isl_surf_get_ccs_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *ccs_surf, - uint32_t row_pitch) + uint32_t row_pitch_B) { assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE); assert(ISL_DEV_GEN(dev) >= 7); @@ -1767,7 +1767,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev, .levels = surf->levels, .array_len = surf->logical_level0_px.array_len, .samples = 1, - .row_pitch = row_pitch, + .row_pitch_B = row_pitch_B, .usage = ISL_SURF_USAGE_CCS_BIT, .tiling_flags = ISL_TILING_CCS_BIT); } @@ -2171,7 +2171,7 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf, uint32_t x_offset_el, y_offset_el; isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb, - surf->row_pitch, + surf->row_pitch_B, total_x_offset_el, total_y_offset_el, offset_B, @@ -2226,7 +2226,7 @@ isl_surf_get_image_surf(const struct isl_device *dev, .levels = 1, .array_len = 1, .samples = surf->samples, - .row_pitch = surf->row_pitch, + .row_pitch_B = surf->row_pitch_B, .usage = usage, .tiling_flags = (1 << surf->tiling)); assert(ok); @@ -2235,7 +2235,7 @@ isl_surf_get_image_surf(const struct isl_device *dev, void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t bpb, - uint32_t row_pitch, + uint32_t row_pitch_B, uint32_t total_x_offset_el, uint32_t total_y_offset_el, uint32_t *base_address_offset, @@ -2244,7 +2244,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, { if (tiling == ISL_TILING_LINEAR) { assert(bpb % 8 == 0); - *base_address_offset = total_y_offset_el * row_pitch + + *base_address_offset = total_y_offset_el * row_pitch_B + total_x_offset_el * (bpb / 8); *x_offset_el = 0; *y_offset_el = 0; @@ -2254,7 +2254,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, struct isl_tile_info tile_info; isl_tiling_get_info(tiling, bpb, &tile_info); - assert(row_pitch % tile_info.phys_extent_B.width == 0); + assert(row_pitch_B % tile_info.phys_extent_B.width == 0); /* For non-power-of-two formats, we need the address to be both tile and * element-aligned. The easiest way to achieve this is to work with a tile @@ -2277,7 +2277,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h; *base_address_offset = - y_offset_tl * tile_info.phys_extent_B.h * row_pitch + + y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B + x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w; } diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 6800b1d76a6..d53c69adbde 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1085,7 +1085,7 @@ struct isl_tile_info { * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but * its physical size is 128B x 32rows, the same as a Y-tile. * - * @see isl_surf::row_pitch + * @see isl_surf::row_pitch_B */ struct isl_extent2d phys_extent_B; }; @@ -1135,13 +1135,13 @@ struct isl_surf_init_info { uint32_t samples; /** Lower bound for isl_surf::alignment, in bytes. */ - uint32_t min_alignment; + uint32_t min_alignment_B; /** * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init() * will fail if this is misaligned or out of bounds. */ - uint32_t row_pitch; + uint32_t row_pitch_B; isl_surf_usage_flags_t usage; @@ -1184,17 +1184,17 @@ struct isl_surf { uint32_t samples; /** Total size of the surface, in bytes. */ - uint64_t size; + uint64_t size_B; /** Required alignment for the surface's base address. */ - uint32_t alignment; + uint32_t alignment_B; /** * The interpretation of this field depends on the value of * isl_tile_info::physical_extent_B. In particular, the width of the - * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width + * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width * and the distance in bytes between vertically adjacent tiles in the image - * is given by row_pitch * isl_tile_info::physical_extent_B.height. + * is given by row_pitch_B * isl_tile_info::physical_extent_B.height. * * For linear images where isl_tile_info::physical_extent_B.height == 1, * this cleanly reduces to being the distance, in bytes, between vertically @@ -1202,7 +1202,7 @@ struct isl_surf { * * @see isl_tile_info::phys_extent_B; */ - uint32_t row_pitch; + uint32_t row_pitch_B; /** * Pitch between physical array slices, in rows of surface elements. @@ -1338,7 +1338,7 @@ struct isl_buffer_fill_state_info { /** * The size of the buffer */ - uint64_t size; + uint64_t size_B; /** * The Memory Object Control state for the filled surface state. @@ -1355,7 +1355,7 @@ struct isl_buffer_fill_state_info { */ enum isl_format format; - uint32_t stride; + uint32_t stride_B; }; struct isl_depth_stencil_hiz_emit_info { @@ -1805,7 +1805,7 @@ bool isl_surf_get_ccs_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *ccs_surf, - uint32_t row_pitch /**< Ignored if 0 */); + uint32_t row_pitch_B /**< Ignored if 0 */); #define isl_surf_fill_state(dev, state, ...) \ isl_surf_fill_state_s((dev), (state), \ @@ -1875,9 +1875,9 @@ isl_surf_get_image_alignment_sa(const struct isl_surf *surf) * Pitch between vertically adjacent surface elements, in bytes. */ static inline uint32_t -isl_surf_get_row_pitch(const struct isl_surf *surf) +isl_surf_get_row_pitch_B(const struct isl_surf *surf) { - return surf->row_pitch; + return surf->row_pitch_B; } /** @@ -1888,8 +1888,8 @@ isl_surf_get_row_pitch_el(const struct isl_surf *surf) { const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - assert(surf->row_pitch % (fmtl->bpb / 8) == 0); - return surf->row_pitch / (fmtl->bpb / 8); + assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0); + return surf->row_pitch_B / (fmtl->bpb / 8); } /** @@ -1927,7 +1927,7 @@ isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) static inline uint32_t isl_surf_get_array_pitch(const struct isl_surf *surf) { - return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; + return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B; } /** @@ -2019,7 +2019,7 @@ isl_surf_get_image_surf(const struct isl_device *dev, void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t bpb, - uint32_t row_pitch, + uint32_t row_pitch_B, uint32_t total_x_offset_el, uint32_t total_y_offset_el, uint32_t *base_address_offset, @@ -2029,7 +2029,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, static inline void isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, enum isl_format format, - uint32_t row_pitch, + uint32_t row_pitch_B, uint32_t total_x_offset_sa, uint32_t total_y_offset_sa, uint32_t *base_address_offset, @@ -2047,7 +2047,7 @@ isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw; const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh; - isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch, + isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B, total_x_offset, total_y_offset, base_address_offset, x_offset_sa, y_offset_sa); diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 51b3f005c01..9cf5a476687 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -104,7 +104,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, db.MIPMapLayoutMode = MIPLAYOUT_BELOW; #endif - db.SurfacePitch = info->depth_surf->row_pitch - 1; + db.SurfacePitch = info->depth_surf->row_pitch_B - 1; #if GEN_GEN >= 8 db.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2; @@ -140,7 +140,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #if GEN_GEN >= 6 sb.StencilBufferMOCS = info->mocs; #endif - sb.SurfacePitch = info->stencil_surf->row_pitch - 1; + sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1; #if GEN_GEN >= 8 sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2; @@ -162,7 +162,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, hiz.SurfaceBaseAddress = info->hiz_address; hiz.HierarchicalDepthBufferMOCS = info->mocs; - hiz.SurfacePitch = info->hiz_surf->row_pitch - 1; + hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1; #if GEN_GEN >= 8 /* From the SKL PRM Vol2a: * diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c index c36985af127..f8bb5275358 100644 --- a/src/intel/isl/isl_storage_image.c +++ b/src/intel/isl/isl_storage_image.c @@ -249,7 +249,7 @@ isl_surf_fill_image_param(const struct isl_device *dev, const int cpp = isl_format_get_layout(surf->format)->bpb / 8; param->stride[0] = cpp; - param->stride[1] = surf->row_pitch / cpp; + param->stride[1] = surf->row_pitch_B / cpp; const struct isl_extent3d image_align_sa = isl_surf_get_image_alignment_sa(surf); diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index f181c3dfb2f..7ab260d701b 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -430,7 +430,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, /* For gen9 1-D textures, surface pitch is ignored */ s.SurfacePitch = 0; } else { - s.SurfacePitch = info->surf->row_pitch - 1; + s.SurfacePitch = info->surf->row_pitch_B - 1; } #if GEN_GEN >= 8 @@ -536,7 +536,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, struct isl_tile_info tile_info; isl_surf_get_tile_info(info->aux_surf, &tile_info); uint32_t pitch_in_tiles = - info->aux_surf->row_pitch / tile_info.phys_extent_B.width; + info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width; s.AuxiliarySurfaceBaseAddress = info->aux_address; s.AuxiliarySurfacePitch = pitch_in_tiles - 1; @@ -658,7 +658,7 @@ void isl_genX(buffer_fill_state_s)(void *state, const struct isl_buffer_fill_state_info *restrict info) { - uint64_t buffer_size = info->size; + uint64_t buffer_size = info->size_B; /* Uniform and Storage buffers need to have surface size not less that the * aligned 32-bit size of the buffer. To calculate the array lenght on @@ -672,13 +672,13 @@ isl_genX(buffer_fill_state_s)(void *state, * buffer_size = (surface_size & ~3) - (surface_size & 3) */ if (info->format == ISL_FORMAT_RAW || - info->stride < isl_format_get_layout(info->format)->bpb / 8) { - assert(info->stride == 1); + info->stride_B < isl_format_get_layout(info->format)->bpb / 8) { + assert(info->stride_B == 1); uint64_t aligned_size = isl_align(buffer_size, 4); buffer_size = aligned_size + (aligned_size - buffer_size); } - uint32_t num_elements = buffer_size / info->stride; + uint32_t num_elements = buffer_size / info->stride_B; if (GEN_GEN >= 7) { /* From the IVB PRM, SURFACE_STATE::Height, @@ -721,7 +721,7 @@ isl_genX(buffer_fill_state_s)(void *state, s.Depth = ((num_elements - 1) >> 20) & 0x7f; #endif - s.SurfacePitch = info->stride - 1; + s.SurfacePitch = info->stride_B - 1; #if GEN_GEN >= 6 s.NumberofMultisamples = MULTISAMPLECOUNT_1; diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c index 16c80c312e9..703f176c6b3 100644 --- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c +++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -153,7 +153,7 @@ test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void) isl_surf_get_array_pitch_sa_rows(&surf)); /* Row pitch should be minimal possible */ - t_assert(surf.row_pitch == 2048); + t_assert(surf.row_pitch_B == 2048); t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0 t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512 @@ -201,7 +201,7 @@ test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void) isl_surf_get_array_pitch_sa_rows(&surf)); /* Row pitch should be minimal possible */ - t_assert(surf.row_pitch == 4096); + t_assert(surf.row_pitch_B == 4096); for (uint32_t a = 0; a < 6; ++a) { uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf); diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 9ab291eabec..a1c359cf461 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -168,7 +168,7 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device, .levels = 1, .array_len = 1, .samples = 1, - .row_pitch = row_pitch, + .row_pitch_B = row_pitch, .usage = ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_RENDER_TARGET_BIT, .tiling_flags = ISL_TILING_LINEAR_BIT); diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 4219a073d2d..2286df6331a 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -2279,7 +2279,7 @@ VkResult anv_AllocateMemory( const uint32_t i915_tiling = isl_tiling_to_i915_tiling(image->planes[0].surface.isl.tiling); int ret = anv_gem_set_tiling(device, mem->bo->gem_handle, - image->planes[0].surface.isl.row_pitch, + image->planes[0].surface.isl.row_pitch_B, i915_tiling); if (ret) { anv_bo_cache_release(device, &device->bo_cache, mem->bo); @@ -2897,9 +2897,9 @@ anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state state, isl_buffer_fill_state(&device->isl_dev, state.map, .address = anv_address_physical(address), .mocs = device->default_mocs, - .size = range, + .size_B = range, .format = format, - .stride = stride); + .stride_B = stride); anv_state_flush(device, state); } diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index a3aecb93901..b0d8c560adb 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -135,24 +135,25 @@ get_surface(struct anv_image *image, VkImageAspectFlagBits aspect) static void add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane) { - assert(surf->isl.size > 0); /* isl surface must be initialized */ + assert(surf->isl.size_B > 0); /* isl surface must be initialized */ if (image->disjoint) { - surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment); + surf->offset = align_u32(image->planes[plane].size, + surf->isl.alignment_B); /* Plane offset is always 0 when it's disjoint. */ } else { - surf->offset = align_u32(image->size, surf->isl.alignment); + surf->offset = align_u32(image->size, surf->isl.alignment_B); /* Determine plane's offset only once when the first surface is added. */ if (image->planes[plane].size == 0) image->planes[plane].offset = image->size; } - image->size = surf->offset + surf->isl.size; - image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset; + image->size = surf->offset + surf->isl.size_B; + image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset; - image->alignment = MAX2(image->alignment, surf->isl.alignment); + image->alignment = MAX2(image->alignment, surf->isl.alignment_B); image->planes[plane].alignment = MAX2(image->planes[plane].alignment, - surf->isl.alignment); + surf->isl.alignment_B); } @@ -249,7 +250,7 @@ add_aux_state_tracking_buffer(struct anv_image *image, const struct anv_device *device) { assert(image && device); - assert(image->planes[plane].aux_surface.isl.size > 0 && + assert(image->planes[plane].aux_surface.isl.size_B > 0 && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV); /* Compressed images must be tiled and therefore everything should be 4K @@ -348,8 +349,8 @@ make_surface(const struct anv_device *dev, .levels = vk_info->mipLevels, .array_len = vk_info->arrayLayers, .samples = vk_info->samples, - .min_alignment = 0, - .row_pitch = anv_info->stride, + .min_alignment_B = 0, + .row_pitch_B = anv_info->stride, .usage = usage, .tiling_flags = tiling_flags); @@ -377,8 +378,8 @@ make_surface(const struct anv_device *dev, .levels = vk_info->mipLevels, .array_len = vk_info->arrayLayers, .samples = vk_info->samples, - .min_alignment = 0, - .row_pitch = anv_info->stride, + .min_alignment_B = 0, + .row_pitch_B = anv_info->stride, .usage = usage, .tiling_flags = ISL_TILING_ANY_MASK); @@ -413,7 +414,7 @@ make_surface(const struct anv_device *dev, } else if (dev->info.gen == 8 && vk_info->samples > 1) { anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ"); } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) { - assert(image->planes[plane].aux_surface.isl.size == 0); + assert(image->planes[plane].aux_surface.isl.size_B == 0); ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->planes[plane].surface.isl, &image->planes[plane].aux_surface.isl); @@ -439,7 +440,7 @@ make_surface(const struct anv_device *dev, likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0); if (allow_compression) { - assert(image->planes[plane].aux_surface.isl.size == 0); + assert(image->planes[plane].aux_surface.isl.size_B == 0); ok = isl_surf_get_ccs_surf(&dev->isl_dev, &image->planes[plane].surface.isl, &image->planes[plane].aux_surface.isl, 0); @@ -457,7 +458,7 @@ make_surface(const struct anv_device *dev, anv_perf_warn(dev->instance, image, "This image format doesn't support rendering. " "Not allocating an CCS buffer."); - image->planes[plane].aux_surface.isl.size = 0; + image->planes[plane].aux_surface.isl.size_B = 0; return VK_SUCCESS; } @@ -480,7 +481,7 @@ make_surface(const struct anv_device *dev, } } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) { assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT)); - assert(image->planes[plane].aux_surface.isl.size == 0); + assert(image->planes[plane].aux_surface.isl.size_B == 0); ok = isl_surf_get_mcs_surf(&dev->isl_dev, &image->planes[plane].surface.isl, &image->planes[plane].aux_surface.isl); @@ -498,14 +499,14 @@ make_surface(const struct anv_device *dev, */ assert((MAX2(image->planes[plane].surface.offset, image->planes[plane].aux_surface.offset) + - (image->planes[plane].aux_surface.isl.size > 0 ? - image->planes[plane].aux_surface.isl.size : - image->planes[plane].surface.isl.size)) <= + (image->planes[plane].aux_surface.isl.size_B > 0 ? + image->planes[plane].aux_surface.isl.size_B : + image->planes[plane].surface.isl.size_B)) <= (image->planes[plane].offset + image->planes[plane].size)); - if (image->planes[plane].aux_surface.isl.size) { + if (image->planes[plane].aux_surface.isl.size_B) { /* assert(image->planes[plane].fast_clear_state_offset == */ - /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */ + /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */ assert(image->planes[plane].fast_clear_state_offset < (image->planes[plane].offset + image->planes[plane].size)); } @@ -766,7 +767,7 @@ void anv_GetImageSubresourceLayout( assert(__builtin_popcount(subresource->aspectMask) == 1); layout->offset = surface->offset; - layout->rowPitch = surface->isl.row_pitch; + layout->rowPitch = surface->isl.row_pitch_B; layout->depthPitch = isl_surf_get_array_pitch(&surface->isl); layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl); @@ -783,7 +784,7 @@ void anv_GetImageSubresourceLayout( layout->size = layout->rowPitch * anv_minify(image->extent.height, subresource->mipLevel); } else { - layout->size = surface->isl.size; + layout->size = surface->isl.size_B; } } @@ -824,7 +825,7 @@ anv_layout_to_aux_usage(const struct gen_device_info * const devinfo, /* If there is no auxiliary surface allocated, we must use the one and only * main buffer. */ - if (image->planes[plane].aux_surface.isl.size == 0) + if (image->planes[plane].aux_surface.isl.size_B == 0) return ISL_AUX_USAGE_NONE; /* All images that use an auxiliary surface are required to be tiled. */ @@ -948,7 +949,7 @@ anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo, uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); /* If there is no auxiliary surface allocated, there are no fast-clears */ - if (image->planes[plane].aux_surface.isl.size == 0) + if (image->planes[plane].aux_surface.isl.size_B == 0) return ANV_FAST_CLEAR_NONE; /* All images that use an auxiliary surface are required to be tiled. */ @@ -1058,7 +1059,7 @@ anv_image_fill_surface_state(struct anv_device *device, * the primary surface. The shadow surface will be tiled, unlike the main * surface, so it should get significantly better performance. */ - if (image->planes[plane].shadow_surface.isl.size > 0 && + if (image->planes[plane].shadow_surface.isl.size_B > 0 && isl_format_is_compressed(view.format) && (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) { assert(isl_format_is_compressed(surface->isl.format)); @@ -1093,9 +1094,9 @@ anv_image_fill_surface_state(struct anv_device *device, assert(aux_usage == ISL_AUX_USAGE_NONE); isl_buffer_fill_state(&device->isl_dev, state_inout->state.map, .address = anv_address_physical(address), - .size = surface->isl.size, + .size_B = surface->isl.size_B, .format = ISL_FORMAT_RAW, - .stride = 1, + .stride_B = 1, .mocs = device->default_mocs); state_inout->address = address, state_inout->aux_address = ANV_NULL_ADDRESS; diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index d15a91dd014..60f40c7e2ae 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2615,7 +2615,7 @@ anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm); * Subsurface of an anv_image. */ struct anv_surface { - /** Valid only if isl_surf::size > 0. */ + /** Valid only if isl_surf::size_B > 0. */ struct isl_surf isl; /** @@ -2764,7 +2764,7 @@ anv_image_aux_levels(const struct anv_image * const image, VkImageAspectFlagBits aspect) { uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); - return image->planes[plane].aux_surface.isl.size > 0 ? + return image->planes[plane].aux_surface.isl.size_B > 0 ? image->planes[plane].aux_surface.isl.levels : 0; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index a9a8a41ac9d..099c30f3d66 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -948,7 +948,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); - if (image->planes[plane].shadow_surface.isl.size > 0 && + if (image->planes[plane].shadow_surface.isl.size_B > 0 && final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) { /* This surface is a linear compressed image with a tiled shadow surface * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so @@ -3760,7 +3760,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, if (GEN_GEN < 10 && (att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && - image->planes[0].aux_surface.isl.size > 0 && + image->planes[0].aux_surface.isl.size_B > 0 && iview->planes[0].isl.base_level == 0 && iview->planes[0].isl.base_array_layer == 0) { if (att_state->aux_usage != ISL_AUX_USAGE_NONE) { diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 5cf704ff0e9..0895e1f2b7f 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -291,7 +291,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); - OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch_B - 1 : 0) | (depthbuffer_format << 18) | (BRW_TILEWALK_YMAJOR << 26) | (tiled_surface << 27) | diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 944762ec46b..8d21cf5fa70 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -634,9 +634,9 @@ brw_emit_buffer_surface_state(struct brw_context *brw, *out_offset + brw->isl_dev.ss.addr_offset, bo, buffer_offset, reloc_flags), - .size = buffer_size, + .size_B = buffer_size, .format = surface_format, - .stride = pitch, + .stride_B = pitch, .mocs = brw_get_bo_mocs(devinfo, bo)); } @@ -949,7 +949,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) | - (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT); + (mt->surf.row_pitch_B - 1) << BRW_SURFACE_PITCH_SHIFT); surf[4] = brw_get_surface_num_multisamples(mt->surf.samples); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index dae0a91fe4f..d2892c48d3b 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -169,7 +169,7 @@ get_blit_intratile_offset_el(const struct brw_context *brw, uint32_t *y_offset_el) { isl_tiling_get_intratile_offset_el(mt->surf.tiling, - mt->cpp * 8, mt->surf.row_pitch, + mt->cpp * 8, mt->surf.row_pitch_B, total_x_offset_el, total_y_offset_el, base_address_offset, x_offset_el, y_offset_el); @@ -425,11 +425,11 @@ emit_miptree_blit(struct brw_context *brw, if (!emit_copy_blit(brw, src_mt->cpp, - reverse ? -src_mt->surf.row_pitch : - src_mt->surf.row_pitch, + reverse ? -src_mt->surf.row_pitch_B : + src_mt->surf.row_pitch_B, src_mt->bo, src_mt->offset + src_offset, src_mt->surf.tiling, - dst_mt->surf.row_pitch, + dst_mt->surf.row_pitch_B, dst_mt->bo, dst_mt->offset + dst_offset, dst_mt->surf.tiling, src_tile_x, src_tile_y, @@ -715,7 +715,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, uint32_t BR13, CMD; int pitch, cpp; - pitch = mt->surf.row_pitch; + pitch = mt->surf.row_pitch_B; cpp = mt->cpp; DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 36681352ba7..e32641f4098 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -551,7 +551,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, unsigned width0, unsigned height0, unsigned depth0, unsigned num_samples, isl_tiling_flags_t tiling_flags, isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags, - unsigned row_pitch, struct brw_bo *bo) + unsigned row_pitch_B, struct brw_bo *bo) { struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1); if (!mt) @@ -585,7 +585,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, .levels = last_level - first_level + 1, .array_len = target == GL_TEXTURE_3D ? 1 : depth0, .samples = num_samples, - .row_pitch = row_pitch, + .row_pitch_B = row_pitch_B, .usage = isl_usage_flags, .tiling_flags = tiling_flags, }; @@ -606,7 +606,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, init_info.tiling_flags = 1u << ISL_TILING_LINEAR; if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) goto fail; - } else if (need_to_retile_as_x(brw, mt->surf.size, mt->surf.tiling)) { + } else if (need_to_retile_as_x(brw, mt->surf.size_B, mt->surf.tiling)) { init_info.tiling_flags = 1u << ISL_TILING_X; if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) goto fail; @@ -618,15 +618,15 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, * See isl_apply_surface_padding(). */ if (mt->surf.tiling != ISL_TILING_LINEAR) - assert(mt->surf.size % mt->surf.row_pitch == 0); + assert(mt->surf.size_B % mt->surf.row_pitch_B == 0); if (!bo) { mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree", - mt->surf.size, + mt->surf.size_B, BRW_MEMZONE_OTHER, isl_tiling_to_i915_tiling( mt->surf.tiling), - mt->surf.row_pitch, alloc_flags); + mt->surf.row_pitch_B, alloc_flags); if (!mt->bo) goto fail; } else { @@ -808,7 +808,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, if (!mt) return NULL; - assert(bo->size >= mt->surf.size); + assert(bo->size >= mt->surf.size_B); brw_bo_reference(bo); return mt; @@ -925,7 +925,7 @@ create_ccs_buf_for_image(struct brw_context *brw, return false; assert(image->aux_offset < image->bo->size); - assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset); + assert(temp_ccs_surf.size_B <= image->bo->size - image->aux_offset); mt->aux_buf = calloc(sizeof(*mt->aux_buf), 1); if (mt->aux_buf == NULL) @@ -1406,7 +1406,7 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, uint32_t x, uint32_t y) { int cpp = mt->cpp; - uint32_t pitch = mt->surf.row_pitch; + uint32_t pitch = mt->surf.row_pitch_B; switch (mt->surf.tiling) { default: @@ -1580,9 +1580,9 @@ intel_miptree_copy_slice(struct brw_context *brw, DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n", _mesa_get_format_name(src_mt->format), - src_mt, src_x, src_y, src_mt->surf.row_pitch, + src_mt, src_x, src_y, src_mt->surf.row_pitch_B, _mesa_get_format_name(dst_mt->format), - dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch, + dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch_B, width, height); if (!intel_miptree_blit(brw, @@ -1649,7 +1649,7 @@ intel_alloc_aux_buffer(struct brw_context *brw, if (!buf) return false; - uint64_t size = aux_surf->size; + uint64_t size = aux_surf->size_B; const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0; if (has_indirect_clear) { @@ -1678,7 +1678,7 @@ intel_alloc_aux_buffer(struct brw_context *brw, */ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size, BRW_MEMZONE_OTHER, I915_TILING_Y, - aux_surf->row_pitch, alloc_flags); + aux_surf->row_pitch_B, alloc_flags); if (!buf->bo) { free(buf); return NULL; @@ -1696,7 +1696,7 @@ intel_alloc_aux_buffer(struct brw_context *brw, /* Memset the aux_surf portion of the BO. */ if (wants_memset) - memset(map, memset_value, aux_surf->size); + memset(map, memset_value, aux_surf->size_B); /* Zero the indirect clear color to match ::fast_clear_color. */ if (has_indirect_clear) { @@ -1731,7 +1731,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw, const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(mt->aux_buf); - assert(mt->surf.size > 0); + assert(mt->surf.size_B > 0); if (devinfo->gen >= 8 || devinfo->is_haswell) { uint32_t width = minify(mt->surf.phys_level0_sa.width, level); @@ -1776,7 +1776,7 @@ intel_miptree_alloc_aux(struct brw_context *brw, switch (mt->aux_usage) { case ISL_AUX_USAGE_NONE: - aux_surf.size = 0; + aux_surf.size_B = 0; aux_surf_ok = true; break; case ISL_AUX_USAGE_HIZ: @@ -1827,7 +1827,7 @@ intel_miptree_alloc_aux(struct brw_context *brw, assert(aux_surf_ok); /* No work is needed for a zero-sized auxiliary buffer. */ - if (aux_surf.size == 0) + if (aux_surf.size_B == 0) return true; /* Create the aux_state for the auxiliary buffer. */ @@ -2931,7 +2931,7 @@ intel_update_r8stencil(struct brw_context *brw, if (!src || devinfo->gen >= 8) return; - assert(src->surf.size > 0); + assert(src->surf.size_B > 0); if (!mt->r8stencil_mt) { assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */ @@ -3045,7 +3045,7 @@ intel_miptree_map_gtt(struct brw_context *brw, x += image_x; y += image_y; - map->stride = mt->surf.row_pitch; + map->stride = mt->surf.row_pitch_B; map->ptr = base + y * map->stride + x * mt->cpp; } @@ -3105,7 +3105,7 @@ intel_miptree_map_blit(struct brw_context *brw, fprintf(stderr, "Failed to allocate blit temporary\n"); goto fail; } - map->stride = map->linear_mt->surf.row_pitch; + map->stride = map->linear_mt->surf.row_pitch_B; /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless @@ -3189,7 +3189,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, src += mt->offset; - src += image_y * mt->surf.row_pitch; + src += image_y * mt->surf.row_pitch_B; src += image_x * mt->cpp; /* Due to the pixel offsets for the particular image being mapped, our @@ -3197,7 +3197,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, * divisible by 16, then the amount by which it's misaligned will remain * consistent from row to row. */ - assert((mt->surf.row_pitch % 16) == 0); + assert((mt->surf.row_pitch_B % 16) == 0); const int misalignment = ((uintptr_t) src) & 15; /* Create an untiled temporary buffer for the mapping. */ @@ -3213,7 +3213,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, for (uint32_t y = 0; y < map->h; y++) { void *dst_ptr = map->ptr + y * map->stride; - void *src_ptr = src + y * mt->surf.row_pitch; + void *src_ptr = src + y * mt->surf.row_pitch_B; _mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes); } @@ -3240,7 +3240,7 @@ intel_miptree_unmap_s8(struct brw_context *brw, for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch, + ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B, image_x + x + map->x, image_y + y + map->y, brw->has_swizzling); @@ -3282,7 +3282,7 @@ intel_miptree_map_s8(struct brw_context *brw, for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch, + ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B, x + image_x + map->x, y + image_y + map->y, brw->has_swizzling); @@ -3319,15 +3319,15 @@ intel_miptree_unmap_etc(struct brw_context *brw, image_y += map->y; uint8_t *dst = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT) - + image_y * mt->surf.row_pitch + + image_y * mt->surf.row_pitch_B + image_x * mt->cpp; if (mt->etc_format == MESA_FORMAT_ETC1_RGB8) - _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch, + _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch_B, map->ptr, map->stride, map->w, map->h); else - _mesa_unpack_etc2_format(dst, mt->surf.row_pitch, + _mesa_unpack_etc2_format(dst, mt->surf.row_pitch_B, map->ptr, map->stride, map->w, map->h, mt->etc_format, true); @@ -3395,12 +3395,12 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw, for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch, + ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B, x + s_image_x + map->x, y + s_image_y + map->y, brw->has_swizzling); ptrdiff_t z_offset = ((y + z_image_y + map->y) * - (z_mt->surf.row_pitch / 4) + + (z_mt->surf.row_pitch_B / 4) + (x + z_image_x + map->x)); if (map_z32f_x24s8) { @@ -3470,12 +3470,12 @@ intel_miptree_map_depthstencil(struct brw_context *brw, for (uint32_t y = 0; y < map->h; y++) { for (uint32_t x = 0; x < map->w; x++) { int map_x = map->x + x, map_y = map->y + y; - ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch, + ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B, map_x + s_image_x, map_y + s_image_y, brw->has_swizzling); ptrdiff_t z_offset = ((map_y + z_image_y) * - (z_mt->surf.row_pitch / 4) + + (z_mt->surf.row_pitch_B / 4) + (map_x + z_image_x)); uint8_t s = s_map[s_offset]; uint32_t z = z_map[z_offset]; @@ -3640,7 +3640,7 @@ intel_miptree_map(struct brw_context *brw, #if defined(USE_SSE41) } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1 && - (mt->surf.row_pitch % 16 == 0)) { + (mt->surf.row_pitch_B % 16 == 0)) { intel_miptree_map_movntdqa(brw, mt, map, level, slice); #endif } else { diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 08c129a4b8b..708757c47b8 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -719,7 +719,7 @@ intel_miptree_get_clear_color(const struct gen_device_info *devinfo, static inline int intel_miptree_blt_pitch(struct intel_mipmap_tree *mt) { - int pitch = mt->surf.row_pitch; + int pitch = mt->surf.row_pitch_B; if (mt->surf.tiling != ISL_TILING_LINEAR) pitch /= 4; return pitch; diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c index 33ed3eb6f4d..249a077cf99 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c @@ -292,7 +292,7 @@ do_blit_bitmap( struct gl_context *ctx, (GLubyte *)stipple, sz, color, - irb->mt->surf.row_pitch, + irb->mt->surf.row_pitch_B, irb->mt->bo, irb->mt->offset, irb->mt->surf.tiling, diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 6ed7895bc76..492ea7cda95 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -203,7 +203,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, yoffset, yoffset + height, pixels, map + irb->mt->offset, - dst_pitch, irb->mt->surf.row_pitch, + dst_pitch, irb->mt->surf.row_pitch_B, brw->has_swizzling, irb->mt->surf.tiling, mem_copy diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index e9de184cca6..c57fb540488 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -457,7 +457,7 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, level - mt->first_level); image->height = minify(mt->surf.phys_level0_sa.height, level - mt->first_level); - image->pitch = mt->surf.row_pitch; + image->pitch = mt->surf.row_pitch_B; image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, &image->tile_x, @@ -533,7 +533,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, brw_bo_reference(irb->mt->bo); image->width = rb->Width; image->height = rb->Height; - image->pitch = irb->mt->surf.row_pitch; + image->pitch = irb->mt->surf.row_pitch_B; image->dri_format = driGLFormatToImageFormat(image->format); image->has_depthstencil = irb->mt->stencil_mt? true : false; @@ -740,7 +740,7 @@ intel_create_image_common(__DRIscreen *dri_screen, } } else { assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE); - aux_surf.size = 0; + aux_surf.size_B = 0; } /* We request that the bufmgr zero the buffer for us for two reasons: @@ -753,23 +753,23 @@ intel_create_image_common(__DRIscreen *dri_screen, * in the pass-through state which is what we want. */ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", - surf.size + aux_surf.size, + surf.size_B + aux_surf.size_B, BRW_MEMZONE_OTHER, isl_tiling_to_i915_tiling(mod_info->tiling), - surf.row_pitch, BO_ALLOC_ZEROED); + surf.row_pitch_B, BO_ALLOC_ZEROED); if (image->bo == NULL) { free(image); return NULL; } image->width = width; image->height = height; - image->pitch = surf.row_pitch; + image->pitch = surf.row_pitch_B; image->modifier = modifier; - if (aux_surf.size) { - image->aux_offset = surf.size; - image->aux_pitch = aux_surf.row_pitch; - image->aux_size = aux_surf.size; + if (aux_surf.size_B) { + image->aux_offset = surf.size_B; + image->aux_pitch = aux_surf.row_pitch_B; + image->aux_size = aux_surf.size_B; } return image; @@ -1113,7 +1113,7 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, .levels = 1, .array_len = 1, .samples = 1, - .row_pitch = strides[index], + .row_pitch_B = strides[index], .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_STORAGE_BIT, @@ -1124,7 +1124,7 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, return NULL; } - const int end = offsets[index] + surf.size; + const int end = offsets[index] + surf.size_B; if (size < end) size = end; } @@ -1162,9 +1162,9 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, return NULL; } - image->aux_size = aux_surf.size; + image->aux_size = aux_surf.size_B; - const int end = image->aux_offset + aux_surf.size; + const int end = image->aux_offset + aux_surf.size_B; if (size < end) size = end; } else { diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 3d948381f4a..9775f788788 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -294,7 +294,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, yoffset, yoffset + height, map, pixels, - image->mt->surf.row_pitch, src_pitch, + image->mt->surf.row_pitch_B, src_pitch, brw->has_swizzling, image->mt->surf.tiling, mem_copy @@ -417,8 +417,8 @@ intel_set_texture_image_mt(struct brw_context *brw, brw->ctx.Driver.FreeTextureImageBuffer(&brw->ctx, image); intel_texobj->needs_validate = true; - intel_image->base.RowStride = mt->surf.row_pitch / mt->cpp; - assert(mt->surf.row_pitch % mt->cpp == 0); + intel_image->base.RowStride = mt->surf.row_pitch_B / mt->cpp; + assert(mt->surf.row_pitch_B % mt->cpp == 0); intel_miptree_reference(&intel_image->mt, mt); @@ -797,7 +797,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, yoffset, yoffset + height, pixels, map, - dst_pitch, image->mt->surf.row_pitch, + dst_pitch, image->mt->surf.row_pitch_B, brw->has_swizzling, image->mt->surf.tiling, mem_copy |