diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.h | 330 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_vce_50.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/Makefile.sources | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/meson.build | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_buffer.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 278 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_query.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.h | 21 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_streamout.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 1 |
14 files changed, 302 insertions, 347 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h deleted file mode 100644 index 66e9a0b7819..00000000000 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright 2013 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/** - * This file is going to be removed. - */ - -#ifndef R600_PIPE_COMMON_H -#define R600_PIPE_COMMON_H - -#include <stdio.h> - -#include "amd/common/ac_binary.h" - -#include "radeon/radeon_winsys.h" - -#include "util/disk_cache.h" -#include "util/u_blitter.h" -#include "util/list.h" -#include "util/u_range.h" -#include "util/slab.h" -#include "util/u_suballoc.h" -#include "util/u_transfer.h" -#include "util/u_threaded_context.h" - -struct u_log_context; -struct si_screen; -struct si_context; -struct si_perfcounters; -struct tgsi_shader_info; -struct si_qbo_state; - -/* Only 32-bit buffer allocations are supported, gallium doesn't support more - * at the moment. - */ -struct r600_resource { - struct threaded_resource b; - - /* Winsys objects. */ - struct pb_buffer *buf; - uint64_t gpu_address; - /* Memory usage if the buffer placement is optimal. */ - uint64_t vram_usage; - uint64_t gart_usage; - - /* Resource properties. */ - uint64_t bo_size; - unsigned bo_alignment; - enum radeon_bo_domain domains; - enum radeon_bo_flag flags; - unsigned bind_history; - int max_forced_staging_uploads; - - /* The buffer range which is initialized (with a write transfer, - * streamout, DMA, or as a random access target). The rest of - * the buffer is considered invalid and can be mapped unsynchronized. - * - * This allows unsychronized mapping of a buffer range which hasn't - * been used yet. It's for applications which forget to use - * the unsynchronized map flag and expect the driver to figure it out. - */ - struct util_range valid_buffer_range; - - /* For buffers only. This indicates that a write operation has been - * performed by TC L2, but the cache hasn't been flushed. - * Any hw block which doesn't use or bypasses TC L2 should check this - * flag and flush the cache before using the buffer. - * - * For example, TC L2 must be flushed if a buffer which has been - * modified by a shader store instruction is about to be used as - * an index buffer. The reason is that VGT DMA index fetching doesn't - * use TC L2. - */ - bool TC_L2_dirty; - - /* Whether the resource has been exported via resource_get_handle. */ - unsigned external_usage; /* PIPE_HANDLE_USAGE_* */ - - /* Whether this resource is referenced by bindless handles. */ - bool texture_handle_allocated; - bool image_handle_allocated; -}; - -struct r600_transfer { - struct threaded_transfer b; - struct r600_resource *staging; - unsigned offset; -}; - -struct r600_fmask_info { - uint64_t offset; - uint64_t size; - unsigned alignment; - unsigned pitch_in_pixels; - unsigned bank_height; - unsigned slice_tile_max; - unsigned tile_mode_index; - unsigned tile_swizzle; -}; - -struct r600_cmask_info { - uint64_t offset; - uint64_t size; - unsigned alignment; - unsigned slice_tile_max; - uint64_t base_address_reg; -}; - -struct r600_texture { - struct r600_resource resource; - - struct radeon_surf surface; - uint64_t size; - struct r600_texture *flushed_depth_texture; - - /* Colorbuffer compression and fast clear. */ - struct r600_fmask_info fmask; - struct r600_cmask_info cmask; - struct r600_resource *cmask_buffer; - uint64_t dcc_offset; /* 0 = disabled */ - unsigned cb_color_info; /* fast clear enable bit */ - unsigned color_clear_value[2]; - unsigned last_msaa_resolve_target_micro_mode; - unsigned num_level0_transfers; - - /* Depth buffer compression and fast clear. */ - uint64_t htile_offset; - float depth_clear_value; - uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */ - uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */ - enum pipe_format db_render_format:16; - uint8_t stencil_clear_value; - bool tc_compatible_htile:1; - bool depth_cleared:1; /* if it was cleared at least once */ - bool stencil_cleared:1; /* if it was cleared at least once */ - bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */ - bool is_depth:1; - bool db_compatible:1; - bool can_sample_z:1; - bool can_sample_s:1; - - /* We need to track DCC dirtiness, because st/dri usually calls - * flush_resource twice per frame (not a bug) and we don't wanna - * decompress DCC twice. Also, the dirty tracking must be done even - * if DCC isn't used, because it's required by the DCC usage analysis - * for a possible future enablement. - */ - bool separate_dcc_dirty:1; - /* Statistics gathering for the DCC enablement heuristic. */ - bool dcc_gather_statistics:1; - /* Counter that should be non-zero if the texture is bound to a - * framebuffer. - */ - unsigned framebuffers_bound; - /* Whether the texture is a displayable back buffer and needs DCC - * decompression, which is expensive. Therefore, it's enabled only - * if statistics suggest that it will pay off and it's allocated - * separately. It can't be bound as a sampler by apps. Limited to - * target == 2D and last_level == 0. If enabled, dcc_offset contains - * the absolute GPUVM address, not the relative one. - */ - struct r600_resource *dcc_separate_buffer; - /* When DCC is temporarily disabled, the separate buffer is here. */ - struct r600_resource *last_dcc_separate_buffer; - /* Estimate of how much this color buffer is written to in units of - * full-screen draws: ps_invocations / (width * height) - * Shader kills, late Z, and blending with trivial discards make it - * inaccurate (we need to count CB updates, not PS invocations). - */ - unsigned ps_draw_ratio; - /* The number of clears since the last DCC usage analysis. */ - unsigned num_slow_clears; -}; - -struct r600_surface { - struct pipe_surface base; - - /* These can vary with block-compressed textures. */ - uint16_t width0; - uint16_t height0; - - bool color_initialized:1; - bool depth_initialized:1; - - /* Misc. color flags. */ - bool color_is_int8:1; - bool color_is_int10:1; - bool dcc_incompatible:1; - - /* Color registers. */ - unsigned cb_color_info; - unsigned cb_color_view; - unsigned cb_color_attrib; - unsigned cb_color_attrib2; /* GFX9 and later */ - unsigned cb_dcc_control; /* VI and later */ - unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */ - unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */ - unsigned spi_shader_col_format_blend:8; /* blending without alpha. */ - unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */ - - /* DB registers. */ - uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */ - uint64_t db_stencil_base; - uint64_t db_htile_data_base; - unsigned db_depth_info; - unsigned db_z_info; - unsigned db_z_info2; /* GFX9+ */ - unsigned db_depth_view; - unsigned db_depth_size; - unsigned db_depth_slice; - unsigned db_stencil_info; - unsigned db_stencil_info2; /* GFX9+ */ - unsigned db_htile_surface; -}; - -struct si_mmio_counter { - unsigned busy; - unsigned idle; -}; - -union si_mmio_counters { - struct { - /* For global GPU load including SDMA. */ - struct si_mmio_counter gpu; - - /* GRBM_STATUS */ - struct si_mmio_counter spi; - struct si_mmio_counter gui; - struct si_mmio_counter ta; - struct si_mmio_counter gds; - struct si_mmio_counter vgt; - struct si_mmio_counter ia; - struct si_mmio_counter sx; - struct si_mmio_counter wd; - struct si_mmio_counter bci; - struct si_mmio_counter sc; - struct si_mmio_counter pa; - struct si_mmio_counter db; - struct si_mmio_counter cp; - struct si_mmio_counter cb; - - /* SRBM_STATUS2 */ - struct si_mmio_counter sdma; - - /* CP_STAT */ - struct si_mmio_counter pfp; - struct si_mmio_counter meq; - struct si_mmio_counter me; - struct si_mmio_counter surf_sync; - struct si_mmio_counter cp_dma; - struct si_mmio_counter scratch_ram; - } named; - unsigned array[0]; -}; - -struct r600_memory_object { - struct pipe_memory_object b; - struct pb_buffer *buf; - uint32_t stride; - uint32_t offset; -}; - -/* This encapsulates a state or an operation which can emitted into the GPU - * command stream. */ -struct r600_atom { - void (*emit)(struct si_context *ctx, struct r600_atom *state); - unsigned short id; -}; - -/* Saved CS data for debugging features. */ -struct radeon_saved_cs { - uint32_t *ib; - unsigned num_dw; - - struct radeon_bo_list_item *bo_list; - unsigned bo_count; -}; - -/* r600_perfcounters.c */ -void si_perfcounters_destroy(struct si_screen *sscreen); - - -/* Inline helpers. */ - -static inline struct r600_resource *r600_resource(struct pipe_resource *r) -{ - return (struct r600_resource*)r; -} - -static inline void -r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res) -{ - pipe_resource_reference((struct pipe_resource **)ptr, - (struct pipe_resource *)res); -} - -static inline void -r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res) -{ - pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b); -} - -static inline bool -vi_dcc_enabled(struct r600_texture *tex, unsigned level) -{ - return tex->dcc_offset && level < tex->surface.num_dcc_levels; -} - -#endif diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c index 04e9d7f5e19..66b54dab25a 100644 --- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c +++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c @@ -34,7 +34,7 @@ #include "vl/vl_video_buffer.h" -#include "r600_pipe_common.h" +#include "si_pipe.h" #include "radeon_video.h" #include "radeon_vce.h" diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c b/src/gallium/drivers/radeon/radeon_vce_50.c index b4f9771ecc6..f4cbc9bb82b 100644 --- a/src/gallium/drivers/radeon/radeon_vce_50.c +++ b/src/gallium/drivers/radeon/radeon_vce_50.c @@ -34,7 +34,7 @@ #include "vl/vl_video_buffer.h" -#include "r600_pipe_common.h" +#include "si_pipe.h" #include "radeon_video.h" #include "radeon_vce.h" diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c index 07493d806ee..143721211db 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c @@ -34,7 +34,7 @@ #include "vl/vl_video_buffer.h" -#include "r600_pipe_common.h" +#include "si_pipe.h" #include "radeon_video.h" #include "radeon_vcn_enc.h" diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources index b20a5497f5e..f760b5b7a69 100644 --- a/src/gallium/drivers/radeonsi/Makefile.sources +++ b/src/gallium/drivers/radeonsi/Makefile.sources @@ -47,7 +47,6 @@ C_SOURCES := \ si_texture.c \ si_uvd.c \ ../radeon/r600_perfcounter.c \ - ../radeon/r600_pipe_common.h \ ../radeon/radeon_uvd.c \ ../radeon/radeon_uvd.h \ ../radeon/radeon_vcn_dec.c \ diff --git a/src/gallium/drivers/radeonsi/meson.build b/src/gallium/drivers/radeonsi/meson.build index f817d591fbe..90498398f38 100644 --- a/src/gallium/drivers/radeonsi/meson.build +++ b/src/gallium/drivers/radeonsi/meson.build @@ -63,7 +63,6 @@ files_libradeonsi = files( 'si_texture.c', 'si_uvd.c', '../radeon/r600_perfcounter.c', - '../radeon/r600_pipe_common.h', '../radeon/radeon_uvd.c', '../radeon/radeon_uvd.h', '../radeon/radeon_vcn_enc_1_2.c', diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index d17b2c6a831..a0855db571f 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -25,6 +25,7 @@ #include "radeonsi/si_pipe.h" #include "util/u_memory.h" #include "util/u_upload_mgr.h" +#include "util/u_transfer.h" #include <inttypes.h> #include <stdio.h> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 3eb89ff0287..971ff19d799 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -29,6 +29,7 @@ #include "sid.h" #include "radeon/radeon_uvd.h" +#include "util/disk_cache.h" #include "util/hash_table.h" #include "util/u_log.h" #include "util/u_memory.h" diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 24221d0a55a..2ed764bd097 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -26,9 +26,12 @@ #define SI_PIPE_H #include "si_shader.h" +#include "si_state.h" #include "util/u_dynarray.h" #include "util/u_idalloc.h" +#include "util/u_range.h" +#include "util/u_threaded_context.h" #ifdef PIPE_ARCH_BIG_ENDIAN #define SI_BIG_ENDIAN 1 @@ -170,6 +173,245 @@ struct si_compute; struct hash_table; struct u_suballocator; +/* Only 32-bit buffer allocations are supported, gallium doesn't support more + * at the moment. + */ +struct r600_resource { + struct threaded_resource b; + + /* Winsys objects. */ + struct pb_buffer *buf; + uint64_t gpu_address; + /* Memory usage if the buffer placement is optimal. */ + uint64_t vram_usage; + uint64_t gart_usage; + + /* Resource properties. */ + uint64_t bo_size; + unsigned bo_alignment; + enum radeon_bo_domain domains; + enum radeon_bo_flag flags; + unsigned bind_history; + int max_forced_staging_uploads; + + /* The buffer range which is initialized (with a write transfer, + * streamout, DMA, or as a random access target). The rest of + * the buffer is considered invalid and can be mapped unsynchronized. + * + * This allows unsychronized mapping of a buffer range which hasn't + * been used yet. It's for applications which forget to use + * the unsynchronized map flag and expect the driver to figure it out. + */ + struct util_range valid_buffer_range; + + /* For buffers only. This indicates that a write operation has been + * performed by TC L2, but the cache hasn't been flushed. + * Any hw block which doesn't use or bypasses TC L2 should check this + * flag and flush the cache before using the buffer. + * + * For example, TC L2 must be flushed if a buffer which has been + * modified by a shader store instruction is about to be used as + * an index buffer. The reason is that VGT DMA index fetching doesn't + * use TC L2. + */ + bool TC_L2_dirty; + + /* Whether the resource has been exported via resource_get_handle. */ + unsigned external_usage; /* PIPE_HANDLE_USAGE_* */ + + /* Whether this resource is referenced by bindless handles. */ + bool texture_handle_allocated; + bool image_handle_allocated; +}; + +struct r600_transfer { + struct threaded_transfer b; + struct r600_resource *staging; + unsigned offset; +}; + +struct r600_fmask_info { + uint64_t offset; + uint64_t size; + unsigned alignment; + unsigned pitch_in_pixels; + unsigned bank_height; + unsigned slice_tile_max; + unsigned tile_mode_index; + unsigned tile_swizzle; +}; + +struct r600_cmask_info { + uint64_t offset; + uint64_t size; + unsigned alignment; + unsigned slice_tile_max; + uint64_t base_address_reg; +}; + +struct r600_texture { + struct r600_resource resource; + + struct radeon_surf surface; + uint64_t size; + struct r600_texture *flushed_depth_texture; + + /* Colorbuffer compression and fast clear. */ + struct r600_fmask_info fmask; + struct r600_cmask_info cmask; + struct r600_resource *cmask_buffer; + uint64_t dcc_offset; /* 0 = disabled */ + unsigned cb_color_info; /* fast clear enable bit */ + unsigned color_clear_value[2]; + unsigned last_msaa_resolve_target_micro_mode; + unsigned num_level0_transfers; + + /* Depth buffer compression and fast clear. */ + uint64_t htile_offset; + float depth_clear_value; + uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */ + uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */ + enum pipe_format db_render_format:16; + uint8_t stencil_clear_value; + bool tc_compatible_htile:1; + bool depth_cleared:1; /* if it was cleared at least once */ + bool stencil_cleared:1; /* if it was cleared at least once */ + bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */ + bool is_depth:1; + bool db_compatible:1; + bool can_sample_z:1; + bool can_sample_s:1; + + /* We need to track DCC dirtiness, because st/dri usually calls + * flush_resource twice per frame (not a bug) and we don't wanna + * decompress DCC twice. Also, the dirty tracking must be done even + * if DCC isn't used, because it's required by the DCC usage analysis + * for a possible future enablement. + */ + bool separate_dcc_dirty:1; + /* Statistics gathering for the DCC enablement heuristic. */ + bool dcc_gather_statistics:1; + /* Counter that should be non-zero if the texture is bound to a + * framebuffer. + */ + unsigned framebuffers_bound; + /* Whether the texture is a displayable back buffer and needs DCC + * decompression, which is expensive. Therefore, it's enabled only + * if statistics suggest that it will pay off and it's allocated + * separately. It can't be bound as a sampler by apps. Limited to + * target == 2D and last_level == 0. If enabled, dcc_offset contains + * the absolute GPUVM address, not the relative one. + */ + struct r600_resource *dcc_separate_buffer; + /* When DCC is temporarily disabled, the separate buffer is here. */ + struct r600_resource *last_dcc_separate_buffer; + /* Estimate of how much this color buffer is written to in units of + * full-screen draws: ps_invocations / (width * height) + * Shader kills, late Z, and blending with trivial discards make it + * inaccurate (we need to count CB updates, not PS invocations). + */ + unsigned ps_draw_ratio; + /* The number of clears since the last DCC usage analysis. */ + unsigned num_slow_clears; +}; + +struct r600_surface { + struct pipe_surface base; + + /* These can vary with block-compressed textures. */ + uint16_t width0; + uint16_t height0; + + bool color_initialized:1; + bool depth_initialized:1; + + /* Misc. color flags. */ + bool color_is_int8:1; + bool color_is_int10:1; + bool dcc_incompatible:1; + + /* Color registers. */ + unsigned cb_color_info; + unsigned cb_color_view; + unsigned cb_color_attrib; + unsigned cb_color_attrib2; /* GFX9 and later */ + unsigned cb_dcc_control; /* VI and later */ + unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */ + unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */ + unsigned spi_shader_col_format_blend:8; /* blending without alpha. */ + unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */ + + /* DB registers. */ + uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */ + uint64_t db_stencil_base; + uint64_t db_htile_data_base; + unsigned db_depth_info; + unsigned db_z_info; + unsigned db_z_info2; /* GFX9+ */ + unsigned db_depth_view; + unsigned db_depth_size; + unsigned db_depth_slice; + unsigned db_stencil_info; + unsigned db_stencil_info2; /* GFX9+ */ + unsigned db_htile_surface; +}; + +struct si_mmio_counter { + unsigned busy; + unsigned idle; +}; + +union si_mmio_counters { + struct { + /* For global GPU load including SDMA. */ + struct si_mmio_counter gpu; + + /* GRBM_STATUS */ + struct si_mmio_counter spi; + struct si_mmio_counter gui; + struct si_mmio_counter ta; + struct si_mmio_counter gds; + struct si_mmio_counter vgt; + struct si_mmio_counter ia; + struct si_mmio_counter sx; + struct si_mmio_counter wd; + struct si_mmio_counter bci; + struct si_mmio_counter sc; + struct si_mmio_counter pa; + struct si_mmio_counter db; + struct si_mmio_counter cp; + struct si_mmio_counter cb; + + /* SRBM_STATUS2 */ + struct si_mmio_counter sdma; + + /* CP_STAT */ + struct si_mmio_counter pfp; + struct si_mmio_counter meq; + struct si_mmio_counter me; + struct si_mmio_counter surf_sync; + struct si_mmio_counter cp_dma; + struct si_mmio_counter scratch_ram; + } named; + unsigned array[0]; +}; + +struct r600_memory_object { + struct pipe_memory_object b; + struct pb_buffer *buf; + uint32_t stride; + uint32_t offset; +}; + +/* Saved CS data for debugging features. */ +struct radeon_saved_cs { + uint32_t *ib; + unsigned num_dw; + + struct radeon_bo_list_item *bo_list; + unsigned bo_count; +}; + struct si_screen { struct pipe_screen b; struct radeon_winsys *ws; @@ -975,6 +1217,9 @@ unsigned si_end_counter(struct si_screen *sscreen, unsigned type, /* si_compute.c */ void si_init_compute_functions(struct si_context *sctx); +/* r600_perfcounters.c */ +void si_perfcounters_destroy(struct si_screen *sscreen); + /* si_perfcounters.c */ void si_init_perfcounters(struct si_screen *screen); @@ -1060,6 +1305,39 @@ void si_init_context_texture_functions(struct si_context *sctx); * common helpers */ +static inline struct r600_resource *r600_resource(struct pipe_resource *r) +{ + return (struct r600_resource*)r; +} + +static inline void +r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res) +{ + pipe_resource_reference((struct pipe_resource **)ptr, + (struct pipe_resource *)res); +} + +static inline void +r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res) +{ + pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b); +} + +static inline bool +vi_dcc_enabled(struct r600_texture *tex, unsigned level) +{ + return tex->dcc_offset && level < tex->surface.num_dcc_levels; +} + +static inline unsigned +si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) +{ + if (stencil) + return rtex->surface.u.legacy.stencil_tiling_index[level]; + else + return rtex->surface.u.legacy.tiling_index[level]; +} + static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r) { diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 3de47c056b2..c859cd081ca 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -29,6 +29,7 @@ #include "util/u_memory.h" #include "util/u_upload_mgr.h" #include "util/os_time.h" +#include "util/u_suballoc.h" #include "tgsi/tgsi_text.h" #include "amd/common/sid.h" diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 7734bfd2f5d..c26ccafdd69 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -134,14 +134,19 @@ #include <llvm-c/Core.h> /* LLVMModuleRef */ #include <llvm-c/TargetMachine.h> #include "tgsi/tgsi_scan.h" +#include "util/u_inlines.h" #include "util/u_queue.h" #include "ac_binary.h" #include "ac_llvm_build.h" -#include "si_state.h" + +#include <stdio.h> struct nir_shader; +struct si_shader; +struct si_context; +#define SI_MAX_ATTRIBS 16 #define SI_MAX_VS_OUTPUTS 40 /* Shader IO unique indices are supported for TGSI_SEMANTIC_GENERIC with an diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index e9849a992f0..628cce87ef9 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -26,14 +26,13 @@ #define SI_STATE_H #include "si_pm4.h" -#include "radeon/r600_pipe_common.h" #include "pipebuffer/pb_slab.h" +#include "util/u_blitter.h" #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1) #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1) -#define SI_MAX_ATTRIBS 16 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */ #define SI_NUM_CONST_BUFFERS 16 @@ -43,6 +42,15 @@ struct si_screen; struct si_shader; struct si_shader_selector; +struct r600_texture; +struct si_qbo_state; + +/* This encapsulates a state or an operation which can emitted into the GPU + * command stream. */ +struct r600_atom { + void (*emit)(struct si_context *ctx, struct r600_atom *state); + unsigned short id; +}; struct si_state_blend { struct si_pm4_state pm4; @@ -448,15 +456,6 @@ void si_update_prims_generated_query_state(struct si_context *sctx, void si_init_streamout_functions(struct si_context *sctx); -static inline unsigned -si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) -{ - if (stencil) - return rtex->surface.u.legacy.stencil_tiling_index[level]; - else - return rtex->surface.u.legacy.tiling_index[level]; -} - static inline unsigned si_get_constbuf_slot(unsigned slot) { /* Constant buffers are in slots [16..31], ascending */ diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index e77eafe8388..4cd5d2fc6b3 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -25,6 +25,7 @@ #include "si_build_pm4.h" #include "util/u_memory.h" +#include "util/u_suballoc.h" static void si_set_streamout_enable(struct si_context *sctx, bool enable); diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index ca8073ae84d..c07a580cd47 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -31,6 +31,7 @@ #include "util/u_pack_color.h" #include "util/u_resource.h" #include "util/u_surface.h" +#include "util/u_transfer.h" #include "util/os_time.h" #include <errno.h> #include <inttypes.h> |