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-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c15
-rw-r--r--src/mesa/drivers/dri/i965/intel_copy_image.c19
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c14
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h2
4 files changed, 15 insertions, 35 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e8a92dde8a9..a95ac95f15d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -395,6 +395,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
+ mt->total_width /= bw;
mt->total_height = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
@@ -419,7 +420,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
/* Layout_below: step right after second mipmap.
*/
if (level == mt->first_level + 1) {
- x += ALIGN_NPOT(width, mt->align_w);
+ x += ALIGN_NPOT(width, mt->align_w) / bw;
} else {
y += img_height;
}
@@ -579,12 +580,14 @@ static void
brw_miptree_layout_texture_3d(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- unsigned yscale = mt->compressed ? 4 : 1;
-
mt->total_width = 0;
mt->total_height = 0;
unsigned ysum = 0;
+ unsigned bh, bw;
+
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned WL = MAX2(mt->physical_width0 >> level, 1);
unsigned HL = MAX2(mt->physical_height0 >> level, 1);
@@ -601,9 +604,9 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
unsigned x = (q % (1 << level)) * wL;
unsigned y = ysum + (q >> level) * hL;
- intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
- mt->total_width = MAX2(mt->total_width, x + wL);
- mt->total_height = MAX2(mt->total_height, (y + hL) / yscale);
+ intel_miptree_set_image_offset(mt, level, q, x / bw, y / bh);
+ mt->total_width = MAX2(mt->total_width, (x + wL) / bw);
+ mt->total_height = MAX2(mt->total_height, (y + hL) / bh);
}
ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c b/src/mesa/drivers/dri/i965/intel_copy_image.c
index 3706704bf1a..ac2738f59a0 100644
--- a/src/mesa/drivers/dri/i965/intel_copy_image.c
+++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
@@ -41,7 +41,6 @@ copy_image_with_blitter(struct brw_context *brw,
{
GLuint bw, bh;
uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
- int cpp;
/* The blitter doesn't understand multisampling at all. */
if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
@@ -86,16 +85,6 @@ copy_image_with_blitter(struct brw_context *brw,
src_y /= (int)bh;
src_width /= (int)bw;
src_height /= (int)bh;
-
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- src_image_x /= bw;
-
- cpp = _mesa_get_format_bytes(src_mt->format);
- } else {
- cpp = src_mt->cpp;
}
src_x += src_image_x;
src_y += src_image_y;
@@ -111,18 +100,12 @@ copy_image_with_blitter(struct brw_context *brw,
dst_x /= (int)bw;
dst_y /= (int)bh;
-
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- dst_image_x /= bw;
}
dst_x += dst_image_x;
dst_y += dst_image_y;
return intelEmitCopyBlit(brw,
- cpp,
+ src_mt->cpp,
src_mt->pitch,
src_mt->bo, src_mt->offset,
src_mt->tiling,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 44eb91327d3..0bcbbbcde8f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -313,15 +313,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
mt->disable_aux_buffers = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0;
exec_list_make_empty(&mt->hiz_map);
-
- /* The cpp is bytes per (1, blockheight)-sized block for compressed
- * textures. This is why you'll see divides by blockheight all over
- */
- unsigned bw, bh;
- _mesa_get_format_block_size(format, &bw, &bh);
- assert(_mesa_get_format_bytes(mt->format) % bw == 0);
- mt->cpp = _mesa_get_format_bytes(mt->format) / bw;
-
+ mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
mt->compressed = _mesa_is_format_compressed(format);
mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE;
@@ -1273,7 +1265,7 @@ intel_miptree_copy_slice(struct brw_context *brw,
unsigned int i, j;
_mesa_get_format_block_size(dst_mt->format, &i, &j);
height = ALIGN_NPOT(height, j) / j;
- width = ALIGN_NPOT(width, i);
+ width = ALIGN_NPOT(width, i) / i;
}
/* If it's a packed depth/stencil buffer with separate stencil, the blit
@@ -2105,7 +2097,9 @@ intel_miptree_map_gtt(struct brw_context *brw,
*/
_mesa_get_format_block_size(mt->format, &bw, &bh);
assert(y % bh == 0);
+ assert(x % bw == 0);
y /= bh;
+ x /= bw;
base = intel_miptree_map_raw(brw, mt) + mt->offset;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 790d3129207..c28162a1983 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -390,7 +390,7 @@ struct intel_mipmap_tree
*/
GLuint physical_width0, physical_height0, physical_depth0;
- GLuint cpp; /**< bytes per pixel */
+ GLuint cpp; /**< bytes per pixel (or bytes per block if compressed) */
GLuint num_samples;
bool compressed;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 08:37:25 +0000