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-rw-r--r--src/compiler/nir/nir_lower_wpos_center.c16
-rw-r--r--src/gallium/drivers/iris/iris_screen.c1
-rw-r--r--src/intel/blorp/blorp_blit.c9
-rw-r--r--src/intel/blorp/blorp_clear.c9
-rw-r--r--src/intel/blorp/blorp_nir_builder.h12
-rw-r--r--src/intel/compiler/brw_fs.cpp8
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp9
-rw-r--r--src/intel/compiler/brw_wm_iz.cpp2
-rw-r--r--src/intel/vulkan/anv_pipeline.c3
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c1
11 files changed, 19 insertions, 52 deletions
diff --git a/src/compiler/nir/nir_lower_wpos_center.c b/src/compiler/nir/nir_lower_wpos_center.c
index 3c114936f7e..56a392768b9 100644
--- a/src/compiler/nir/nir_lower_wpos_center.c
+++ b/src/compiler/nir/nir_lower_wpos_center.c
@@ -80,19 +80,9 @@ lower_wpos_center_block(nir_builder *b, nir_block *block,
nir_foreach_instr(instr, block) {
if (instr->type == nir_instr_type_intrinsic) {
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
- if (intr->intrinsic == nir_intrinsic_load_deref) {
- nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
- if (deref->mode != nir_var_shader_in)
- continue;
-
- nir_variable *var = nir_deref_instr_get_variable(deref);
-
- if (var->data.location == VARYING_SLOT_POS) {
- /* gl_FragCoord should not have array/struct derefs: */
- assert(deref->deref_type == nir_deref_type_var);
- update_fragcoord(b, intr, for_sample_shading);
- progress = true;
- }
+ if (intr->intrinsic == nir_intrinsic_load_frag_coord) {
+ update_fragcoord(b, intr, for_sample_shading);
+ progress = true;
}
}
}
diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c
index 2a1a95a2414..2b0136d04d3 100644
--- a/src/gallium/drivers/iris/iris_screen.c
+++ b/src/gallium/drivers/iris/iris_screen.c
@@ -190,6 +190,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
case PIPE_CAP_DRAW_PARAMETERS:
+ case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
case PIPE_CAP_INVALIDATE_BUFFER:
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 78a47c9cbe5..323e94e3d28 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -60,9 +60,6 @@ struct brw_blorp_blit_vars {
nir_variable *v_dst_offset;
nir_variable *v_src_inv_size;
- /* gl_FragCoord */
- nir_variable *frag_coord;
-
/* gl_FragColor */
nir_variable *color_out;
};
@@ -84,10 +81,6 @@ brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
#undef LOAD_INPUT
- v->frag_coord = nir_variable_create(b->shader, nir_var_shader_in,
- glsl_vec4_type(), "gl_FragCoord");
- v->frag_coord->data.location = VARYING_SLOT_POS;
-
v->color_out = nir_variable_create(b->shader, nir_var_shader_out,
glsl_vec4_type(), "gl_FragColor");
v->color_out->data.location = FRAG_RESULT_COLOR;
@@ -98,7 +91,7 @@ blorp_blit_get_frag_coords(nir_builder *b,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
{
- nir_ssa_def *coord = nir_f2i32(b, nir_load_var(b, v->frag_coord));
+ nir_ssa_def *coord = nir_f2i32(b, nir_load_frag_coord(b));
/* Account for destination surface intratile offset
*
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 7e77e80565f..af7c0d506f3 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -70,12 +70,7 @@ blorp_params_get_clear_kernel(struct blorp_batch *batch,
nir_ssa_def *color = nir_load_var(&b, v_color);
if (clear_rgb_as_red) {
- nir_variable *frag_coord =
- nir_variable_create(b.shader, nir_var_shader_in,
- glsl_vec4_type(), "gl_FragCoord");
- frag_coord->data.location = VARYING_SLOT_POS;
-
- nir_ssa_def *pos = nir_f2i32(&b, nir_load_var(&b, frag_coord));
+ nir_ssa_def *pos = nir_f2i32(&b, nir_load_frag_coord(&b));
nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
nir_imm_int(&b, 3));
nir_ssa_def *color_component =
@@ -976,7 +971,7 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
/* Do an MCS fetch and check if it is equal to the magic clear value */
nir_ssa_def *mcs =
- blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, blorp_nir_frag_coord(&b)),
+ blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, nir_load_frag_coord(&b)),
nir_load_layer_id(&b));
nir_ssa_def *is_clear =
blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);
diff --git a/src/intel/blorp/blorp_nir_builder.h b/src/intel/blorp/blorp_nir_builder.h
index 9664bdbcd27..0ba855fcd66 100644
--- a/src/intel/blorp/blorp_nir_builder.h
+++ b/src/intel/blorp/blorp_nir_builder.h
@@ -37,18 +37,6 @@ blorp_nir_init_shader(nir_builder *b,
}
static inline nir_ssa_def *
-blorp_nir_frag_coord(nir_builder *b)
-{
- nir_variable *frag_coord =
- nir_variable_create(b->shader, nir_var_shader_in,
- glsl_vec4_type(), "gl_FragCoord");
-
- frag_coord->data.location = VARYING_SLOT_POS;
-
- return nir_load_var(b, frag_coord);
-}
-
-static inline nir_ssa_def *
blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
{
nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 493b9fdf8bb..c8dae0c85d9 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6822,7 +6822,7 @@ fs_visitor::setup_fs_payload_gen6()
assert(devinfo->gen >= 6);
prog_data->uses_src_depth = prog_data->uses_src_w =
- (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ (nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
prog_data->uses_sample_mask =
(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
@@ -7601,6 +7601,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
emit_shader_time_begin();
if (nir->info.inputs_read > 0 ||
+ (nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) ||
(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
if (devinfo->gen < 6)
emit_interpolation_setup_gen4();
@@ -7707,10 +7708,7 @@ is_used_in_not_interp_frag_coord(nir_ssa_def *def)
return true;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src->parent_instr);
- if (intrin->intrinsic != nir_intrinsic_load_interpolated_input)
- return true;
-
- if (nir_intrinsic_base(intrin) != VARYING_SLOT_POS)
+ if (intrin->intrinsic != nir_intrinsic_load_frag_coord)
return true;
}
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 0b3982737dd..2451fbf0349 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3829,12 +3829,11 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
break;
}
- case nir_intrinsic_load_interpolated_input: {
- if (nir_intrinsic_base(instr) == VARYING_SLOT_POS) {
- emit_fragcoord_interpolation(dest);
- break;
- }
+ case nir_intrinsic_load_frag_coord:
+ emit_fragcoord_interpolation(dest);
+ break;
+ case nir_intrinsic_load_interpolated_input: {
assert(instr->src[0].ssa &&
instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
nir_intrinsic_instr *bary_intrinsic =
diff --git a/src/intel/compiler/brw_wm_iz.cpp b/src/intel/compiler/brw_wm_iz.cpp
index b9b7e70a0f3..c2ea4aafd2b 100644
--- a/src/intel/compiler/brw_wm_iz.cpp
+++ b/src/intel/compiler/brw_wm_iz.cpp
@@ -145,7 +145,7 @@ void fs_visitor::setup_fs_payload_gen4()
payload.subspan_coord_reg[0] = reg++;
prog_data->uses_src_depth =
- (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ (nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
kill_stats_promoted_workaround) {
payload.source_depth_reg[0] = reg;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index c2a164cc802..a9a403f1233 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -167,6 +167,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
};
struct spirv_to_nir_options spirv_options = {
.lower_workgroup_access_to_offsets = true,
+ .frag_coord_is_sysval = true,
.caps = {
.demote_to_helper_invocation = true,
.derivative_group = true,
@@ -652,7 +653,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
- NIR_PASS_V(nir, nir_lower_input_attachments, false);
+ NIR_PASS_V(nir, nir_lower_input_attachments, true);
}
NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 3783d1532e9..91053842aa1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -621,6 +621,7 @@ brw_initialize_context_constants(struct brw_context *brw)
if (devinfo->gen >= 5 || devinfo->is_g4x)
ctx->Const.MaxClipPlanes = 8;
+ ctx->Const.GLSLFragCoordIsSysVal = true;
ctx->Const.GLSLTessLevelsAsInputs = true;
ctx->Const.PrimitiveRestartForPatches = true;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 0e91612d845..b69b032a9c2 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -262,6 +262,7 @@ brwProgramStringNotify(struct gl_context *ctx,
if (newFP == curFP)
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
+ _mesa_program_fragment_position_to_sysval(&newFP->program);
newFP->id = get_new_program_id(brw->screen);
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 03:04:34 +0000