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-rw-r--r--src/amd/common/ac_gpu_info.c32
-rw-r--r--src/amd/common/ac_gpu_info.h1
-rw-r--r--src/amd/vulkan/si_cmd_buffer.c32
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c32
4 files changed, 35 insertions, 62 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 5fb1e26376a..aa09ba815ef 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -538,6 +538,38 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->has_gds_ordered_append = info->chip_class >= GFX7 &&
info->drm_minor >= 29;
+
+ if (info->chip_class >= GFX9) {
+ unsigned pc_lines = 0;
+
+ switch (info->family) {
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ pc_lines = 2048;
+ break;
+ case CHIP_RAVEN:
+ case CHIP_RAVEN2:
+ case CHIP_RENOIR:
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
+ pc_lines = 1024;
+ break;
+ case CHIP_NAVI14:
+ pc_lines = 512;
+ break;
+ default:
+ assert(0);
+ }
+
+ if (info->chip_class >= GFX10) {
+ info->pbb_max_alloc_count = pc_lines / 3;
+ } else {
+ info->pbb_max_alloc_count =
+ MIN2(128, pc_lines / (4 * info->max_se));
+ }
+ }
+
return true;
}
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9986d58202a..555f7175e87 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -66,6 +66,7 @@ struct radeon_info {
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory;
+ uint32_t pbb_max_alloc_count;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index d4369b5739a..9dd328f968f 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -427,38 +427,8 @@ si_emit_graphics(struct radv_physical_device *physical_device,
}
if (physical_device->rad_info.chip_class >= GFX9) {
- unsigned num_se = physical_device->rad_info.max_se;
- unsigned pc_lines = 0;
- unsigned max_alloc_count = 0;
-
- switch (physical_device->rad_info.family) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- pc_lines = 4096;
- break;
- case CHIP_RAVEN:
- case CHIP_RAVEN2:
- case CHIP_RENOIR:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- pc_lines = 1024;
- break;
- case CHIP_NAVI14:
- pc_lines = 512;
- break;
- default:
- assert(0);
- }
-
- if (physical_device->rad_info.chip_class >= GFX10) {
- max_alloc_count = pc_lines / 3;
- } else {
- max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
- }
-
radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
- S_028C48_MAX_ALLOC_COUNT(max_alloc_count - 1) |
+ S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 893968d1997..8e6dd3c335b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5686,38 +5686,8 @@ static void si_init_config(struct si_context *sctx)
RADEON_PRIO_BORDER_COLORS);
if (sctx->chip_class >= GFX9) {
- unsigned num_se = sscreen->info.max_se;
- unsigned pc_lines = 0;
- unsigned max_alloc_count = 0;
-
- switch (sctx->family) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- pc_lines = 2048;
- break;
- case CHIP_RAVEN:
- case CHIP_RAVEN2:
- case CHIP_RENOIR:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- pc_lines = 1024;
- break;
- case CHIP_NAVI14:
- pc_lines = 512;
- break;
- default:
- assert(0);
- }
-
- if (sctx->chip_class >= GFX10) {
- max_alloc_count = pc_lines / 3;
- } else {
- max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
- }
-
si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
- S_028C48_MAX_ALLOC_COUNT(max_alloc_count - 1) |
+ S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));