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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c2
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h1
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c4
3 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 97673ee2250..259ff36800c 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -253,6 +253,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (is_imported)
flags |= RADEON_SURF_IMPORTED;
+ if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+ flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
array_mode, surface);
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 3e30e954574..3027c4a8b53 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -281,6 +281,7 @@ enum radeon_micro_mode {
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
+#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
struct radeon_surf_level {
uint64_t offset;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d65dae72661..d8ab28b36fd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -402,7 +402,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
* requested, because TC-compatible HTILE requires 2D tiling.
*/
AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
- !(flags & RADEON_SURF_FMASK);
+ !AddrSurfInfoIn.flags.fmask &&
+ tex->nr_samples <= 1 &&
+ (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
/* DCC notes:
* - If we add MSAA support, keep in mind that CB can't decompress 8bpp