diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_blorp.cpp | 27 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_urb.c | 23 |
3 files changed, 28 insertions, 30 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 8f20d6ec8c0..6e0e1add5f8 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1153,6 +1153,14 @@ void gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned num_samples); +/* gen7_urb.c */ +void +gen7_allocate_push_constants(struct brw_context *brw); + +void +gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries, + GLuint vs_size, GLuint vs_start); + /*====================================================================== diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index d6eff0024d7..b41717db249 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -50,34 +50,14 @@ static void gen7_blorp_emit_urb_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - /* The minimum valid value is 32. See 3DSTATE_URB_VS, * Dword 1.15:0 "VS Number of URB Entries". */ int num_vs_entries = 32; + int vs_size = 2; + int vs_start = 2; /* skip over push constants */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); - OUT_BATCH(1 << GEN7_URB_ENTRY_SIZE_SHIFT | - 0 << GEN7_URB_STARTING_ADDRESS_SHIFT | - num_vs_entries); - ADVANCE_BATCH(); - - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); - OUT_BATCH(0); - ADVANCE_BATCH(); - - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); - OUT_BATCH(0); - ADVANCE_BATCH(); - - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2)); - OUT_BATCH(0); - ADVANCE_BATCH(); + gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start); } @@ -744,6 +724,7 @@ gen7_blorp_exec(struct intel_context *intel, uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); gen6_blorp_emit_batch_head(brw, params); + gen7_allocate_push_constants(brw); gen6_emit_3dstate_multisample(brw, params->num_samples); gen6_emit_3dstate_sample_mask(brw, params->num_samples); gen6_blorp_emit_state_base_address(brw, params); diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 920c9fc6a77..481497b7129 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -50,7 +50,7 @@ * * See "Volume 2a: 3D Pipeline," section 1.8. */ -static void +void gen7_allocate_push_constants(struct brw_context *brw) { struct intel_context *intel = &brw->intel; @@ -100,31 +100,40 @@ gen7_upload_urb(struct brw_context *brw) assert(!brw->gs.prog_active); gen7_emit_vs_workaround_flush(intel); + gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, brw->urb.vs_size, + brw->urb.vs_start); +} + +void +gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries, + GLuint vs_size, GLuint vs_start) +{ + struct intel_context *intel = &brw->intel; BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); - OUT_BATCH(brw->urb.nr_vs_entries | - ((brw->urb.vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | - (brw->urb.vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); + OUT_BATCH(nr_vs_entries | + ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | + (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(); /* Allocate the GS, HS, and DS zero space - we don't use them. */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | - (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | - (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | - (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(); } |